Commenced in January 2007
Paper Count: 31837
Low Voltage Squarer Using Floating Gate MOSFETs
Abstract:A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1070985Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1805
 I. Filanovsky and H. Baltbs, "Simple CMOS analog square rooting and squaring circuits," IEEE Trans. Circuits Systems - part I, vol.39, no.4, pp. 312-315, 1992.
 S. Liu and Y. Hwang, "CMOS squarer and four-quadrant multiplier," IEEE Trans. Circuits Systems - part I, vol.42, no.2, pp. 119-122, 1992.
 G. Giustolisi, G. Palmisano, and G. Palumbo,"1.5 V power supply CMOS voltage squarer," Electronics Letters, vol.33, no.13, pp. 1134 - 1136, 1997.
 K. Kimura,"A bipolar four-quadrant analog quarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges," IEEE J. Solid-Stare Circuits, vol.29, no.1, pp. 46-55, 1994.
 Y. Liming, S.H.K. Embadi, and E. Sanchez-Sinencio,"A floating gate MOSFET D/A converter," in Proc. IEEE Int. Symp. Circuits Systems, Hong Kong, 1997, pp. 409-412.
 R. Pandey, and M. Gupta,"A New FMOS Voltage-Controlled Resistor," in Proc. IEEE International Conference on Intelligent and Advanced Systems, ICIAS-2007, Malaysia, 2007, pp. 1392-1395.
 R. Pandey, and M. Gupta,"A Novel Voltage-Controlled Grounded Resistor Using FGMOS Technique," in Proc. IEEE International Conference on Multimedia, Signal Processing and Communication Technologies IMPACT-2009, Aligarh, India 2009, pp. 16-19.
 M. Gupta, and R. Pandey, "FGMOS Based Low-Voltage Tunable Floating Resistor," Journal of Active and Passive Electronic Devices, to be published.
 Y. Berg, and T.S. R. Lande, "Programmable floating gate MOS logic for low-power operation," in Proc. IEEE Int. Symp. Circuits Systems, ISCAS-97, Hong Kong, 1997, pp. 1792-1795.
 B.W. Lee, B. J. Sheu, and H. Yang, "Analog floating gate-synapses for general purpose VLSI neural computation," IEEE Trans. Circuits Syst., vol. 38, pp. 654-657, June 1991.
 J. Ramirez-Angulo, S.C. Choi, and G. G. Altamirano, "Low voltage circuits building blocks using multiple input floating gate transistors," IEEE Trans. Circuits Syst. -I, vol. 42, no. 11, pp. 971-974, 1995.
 H. R. Mehrvarz, and C.Y. Kwok, "A novel multi-input floating-gate MOS four-quadrant analog multiplier," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1123-1131, 1996.
 J.F. Schoeman, and T-H. Joubert, "Four quadrant analogue CMOS multiplier using capacitively coupled dual-gate transistors," Electron. Lett., vol. 32, no. 3, pp. 209-210, 1996.
 J. J. Chen, S. I. Liu, and Y. S. Hwang, "Low-voltage single supply four quandrant multiplier using floating-gate MOSFETs," in Proc. IEEE Int. Symp. Circuits Systems, ISCAS-97, Hong Kong, 1997, pp. 237-240.
 S. Vlassis, and S. Siskos, "Analogue squarer and multiplier based on floating-gate MOS transistors," Electron. Lett., vol. 34, no. 9, pp. 825- 826, 1998.
 S. Vlassis, T.Th. Yiamalis, and S. Siskos, "Analogue computational circuits based on floating-gate transistors," in Proc. IEEE Int. Conf. Electr.Circuits Syst. ICECS-99, Greece, 1999, vol. I, pp. 129-133.
 S. Vlassis, and S. Siskos, "Design of voltage-mode and current-mode computational circuits," IEEE Transactions on Circuits and Systems-I, vol. 51, no. 2, pp. 329-341, 2004.
 T. Inoue, H. Nakane, Y. Fukuju, and E.S. Sinencio, "A Design of a Low-voltage Current-Mode Fully- Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation," Analog Integrated Circuits and Signal Processing, vol. 32, pp. 249-256, 2002.
 E.R. Villegas, and H. Barnes, "Solution to trapped charge in FGMOS transistors," Electron. Lett., vol. 39, no. 19, pp. 1416 - 1417, 2003.
 S. Yan, and E. Sanchez-Sinencio, "Low Voltage Analog Circuit Design Techniques: A Tutorial," IEICE Trans. Analog Integrated Circuits and Systems, vol. E00-A, no. 2, pp. 1-17, 2000.