%0 Journal Article
	%A Chih Chin Yang and  Yen Chun Lin and  Hsiao Hsuan Cheng
	%D 2011
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 57, 2011
	%T Influence of Paralleled Capacitance Effect in Well-defined Multiple Value Logical Level System with Active Load
	%U https://publications.waset.org/pdf/12082
	%V 57
	%X Three similar negative differential resistance (NDR)
profiles with both high peak to valley current density ratio (PVCDR)
value and high peak current density (PCD) value in unity resonant
tunneling electronic circuit (RTEC) element is developed in this paper.
The PCD values and valley current density (VCD) values of the three
NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values
of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV
values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR
values reach about 4.4 in three NDR curves. The PCD value of 3.5 A
in triple PVCDR RTEC element is better than other resonant
tunneling devices (RTD) elements. The high PVCDR value is
concluded the lower VCD value about 0.8 A. The low VCD value is
achieved by suitable selection of resistors in triple PVCDR RTEC
element. The low PV value less than 1.35 V possesses low power
dispersion in triple PVCDR RTEC element. The designed multiple
value logical level (MVLL) system using triple PVCDR RTEC
element provides equidistant logical level. The logical levels of
MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low
voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from
high voltage back to low voltage in half cycle of sinusoid wave. The
output level of four levels MVLL system is represented in 0.3 V, 1.1 V,
1.7 V, and 2.6 V, which satisfies the NMP condition of traditional
two-bit system. The remarkable logical characteristic of improved
MVLL system with paralleled capacitor are with four significant
stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV.
The stability and articulation of logical levels of improved MVLL
system are outstanding. The average holding time of improved MVLL
system is approximately 0.14 μs. The holding time of improved
MVLL system is fourfold than of basic MVLL system. The function of
additional capacitor in the improved MVLL system is successfully
	%P 1184 - 1190