Commenced in January 2007
Paper Count: 30135
Very High Speed Data Driven Dynamic NAND Gate at 22nm High K Metal Gate Strained Silicon Technology Node
Abstract:Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1112133Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1251
 T Matsuda, Y Sugiyama et al, “A test structure of channel length engineering of NAND gates in standard cell library”, 2008 IEEE Conference on Microelectronic Test Structures, March 24-27, Edinburgh, UK.
 Martin Taylor, E patchett et al, “organic digital logic and analog circuit fabricated in a roll to roll compatible vacuum evaporation process, IEEE transaction on electron devices, Vol61, No 8, August 2014
 M. De Marchi, J. Zhang, S. Frache, D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, Configurable logic gates using polarity controlled silicon nanowire gate-all-around FETs. IEEE Electron Device Lett. 35, 880–882 (2014)
 Davide De Caro, “Glitch-Free NAND-Based Digitally Controlled Delay-Lines”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No.1, Jan 2013.
 Guerin, M., E. Bergeret, E. Benevent, A. Daami, P. Pannier and R. Coppard, “Organic Complementary Logic Circuits and Volatile Memories Integrated on Plastic Foils” - IEEE Transactions on Electron Devices 60, 2045-2051, June 2013
 Kang-Jun Baeg, Dongyoon Khim, Juhwan Kim, Dong-Yu Kim, Si-Woo Sung, Byung-Do Yang*, Yong-Young Noh*, “Flexible Complementary Logic Gates using Inkjet-Printed Polymer Field-Effect Transistors” IEEE Electron. Device Lett. 2013, 34, 126-128.
 H. Luo, P. Wellenius, L. Lunardi and J. Muth, “Transparent IGZO logic gates”, IEEE Electron Devices Letter, vol. 33, No. 5, pp. 673-675, May 2012.
 Po-Yen Chiu, Ming D K et al, “Design of 2XVDD logic gates with only 1XVDD devices in nanoscale CMOS technology, IEEE conference, SOCC 20137:33-36
 Yang, Wei B L, Yu Yao L, Y Lung, “Analysis and design considerations of static CMOS Logics under process, Voltage and temperature”, proceedings of the 2014 International conference on information science, electronics and electrical engineering (ISEEE, 2014), pp 1653-1656
 Azam Beg, "Designing Array-Based CMOS Logic Gates by Using a Feedback Control System," 2014 IEEE International Conference on Systems, Man and Cybernetics (SMC), San Diego, CA, USA, Oct 2014, pp. 1-5.
 Ramin Rafati, Sied Mehdi, “A 16 bit Barrel Shifter implemented in Data Driven Dynamic logic (D3L)”, IEEE transaction on circuit and system-I, Vol 53 no 10, pp2194-2202, October 2006.