Commenced in January 2007
Paper Count: 30172
New Gate Stack Double Diffusion MOSFET Design to Improve the Electrical Performances for Power Applications
Abstract:In this paper, we have developed an explicit analytical drain current model comprising surface channel potential and threshold voltage in order to explain the advantages of the proposed Gate Stack Double Diffusion (GSDD) MOSFET design over the conventional MOSFET with the same geometric specifications that allow us to use the benefits of the incorporation of the high-k layer between the oxide layer and gate metal aspect on the immunity of the proposed design against the self-heating effects. In order to show the efficiency of our proposed structure, we propose the simulation of the power chopper circuit. The use of the proposed structure to design a power chopper circuit has showed that the (GSDD) MOSFET can improve the working of the circuit in terms of power dissipation and self-heating effect immunity. The results so obtained are in close proximity with the 2D simulated results thus confirming the validity of the proposed model.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1056978Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1231
 R.S. Scott, G.A. Franz, and J.L. Johnson," An accurate model for power DMOSFETs including interelectrode capacitances," IEEE Tran. Power Electron, vol. 6, pp. 192-198, 1991.
 Y. Kim, J.G. Fossum, and R.K. Williams," New Physical Insights and Models for High-Voltage LDMOST IC CAD," IEEE Tran. Electron Devices, vol. 7, pp. 1641-1649, 1991.
 R. Sithanandam and M. J. Kumar," Linearity and speed optimization in SOI LDMOS using gate engineering," Semicond. Sci. Technol, vol. 25, 6pp. 015006, 2010.
 J.G. Fiorenza, and J. A. del Alamo," Experimental Comparison of RF Power LDMOSFETs on Thin-Film SOI and Bulk Silicon," IEEE Trans. Electron Devices, vol. 49, pp. 687-692, 2002.
 R.S. Saxena and M.J. Kumar," Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs," IEEE Trans. Electron Devices, vol. 56, pp. 517-522, 2009.
 A.C.T. Aarts, N. D-Halleweyen, and R. van Langevelde," A Surface- Potential-Based High-Voltage Compact LDMOS Transistor Model," IEEE Trans. Electron Devices, vol. 52, pp. 999-1007, 2005.
 A.C.T. Aarts, W.J. Kloosterman," Compact Modeling of High-Voltage LDMOS Devices Including Quasi-Saturation," IEEE Trans. Electron Devices, vol. 53, pp. 897-902, 2006.
 K. Joardar, K.K. Gullapulli, C.C. McAndrew, M.E. Burnham, and A. Wild," An improved MOSFET model for circuit simulation," IEEE Trans. Electron Devices, vol. 45, pp. 134-148, 1998.
 ATLAS: 2D Device Simulator, SILVACO International 2008.