Search results for: Floating Gate MOSFET

Authors: C. L. Toh, N. R. N. Idris, A. H. M. Yatim

Abstract:

This paper introduces a new digital logic design, which combines the DSP and FPGA to implement the conventional DTC of induction machine. The DSP will be used for floating point calculation whereas the FPGA main task is to implement the hysteresis-based controller. The emphasis is on FPGA digital logic design. The simulation and experimental results are presented and summarized.

Keywords: DTC, DSP, FPGA, induction machine

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Authors: F. Rahmani, F. Razaghian, A. R. Kashaninia

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This article proposes a new method for application in communication circuit systems that increase efficiency, PAE, output power and gain in the circuit. The proposed method is based on a combination of switching class-E and class-J and has been termed class-EJ. This method was investigated using both theory and simulation to confirm ∼72% PAE and output power of >39dBm. The combination and design of the proposed power amplifier accrues gain of over 15dB in the 2.9 to 3.5GHz frequency bandwidth. This circuit was designed using MOSFET and high power transistors. The loadand source-pull method achieved the best input and output networks using lumped elements. The proposed technique was investigated for fundamental and second harmonics having desirable amplitudes for the output signal.

Keywords: Power Amplifier (PA), GaN HEMT, Class-J and Class-E, High Efficiency.

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Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: Z. Harouni, L. Osman, M. Yeddes, A. Gharsallah, H. Baudrand

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In this paper, an efficient wave concept iterative process (WCIP) with auxiliary Sources is presented for full wave investigation of an active microwave structure on micro strip technology. Good agreement between the experimental and simulation results is observed.

Keywords: WCIP, Dual-Gate Transistor, Auxiliary source.

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Authors: Shibesh Dutta, Sivaramakrishnan R., Sundar Gopalan, Balakrishnan Shankar

Abstract:

MOSCAPs of various combinations of Hafnium oxide and Titanium oxide of varying thickness with Aluminum as gate electrode have been fabricated and electrically characterized. The effects of voltage stress on the I-V characteristics for prolonged time durations have been studied and compared. Results showed hard breakdown and negligible degradation of reliability under stress.

Keywords: breakdown, MOSCAP, voltage stress.

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Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

Abstract:

This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: Energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm.

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Authors: Alloysius C. Ogodo, Ositadinma C. Ugbogu, Uzochukwu G. Ekeleme

Abstract:

Food poisoning and infection by bacteria are of public health significance to both developing and developed countries. Samples of ogi (akamu) prepared from white and yellow variety of maize sold in Uturu and Okigwe were analyzed together with the laboratory prepared ogi for bacterial quality using the standard microbiological methods. The analyses showed that both white and yellow variety had total bacterial counts (cfu/g) of 4.0 ×107 and 3.9 x 107 for the laboratory prepared ogi while the commercial ogi had 5.2 x 107 and 4.9 x107, 4.9 x107 and 4.5 x107, 5.4 x107 and 5.0 x107 for Eke-Okigwe, Up-gate and Nkwo-Achara market respectively. The Staphylococcal counts ranged from 2.0 x 102 to 5.0 x102 and 1.0 x 102 to 4.0 x102 for the white and yellow variety from the different markets while Staphylococcal growth was not recorded on the laboratory prepared ogi. The laboratory prepared ogi had no Coliform growth while the commercially prepared ogi had counts of 0.5 x103 to 1.6 x 103 for white variety and 0.3 x 103 to 1.1 x103 for yellow variety respectively. The Lactic acid bacterial count of 3.5x106 and 3.0x106 was recorded for the laboratory ogi while the commercially prepared ogi ranged from 3.2x106 to 4.2x106 (white variety) and 3.0 x106 to 3.9 x106 (yellow). The presence of bacteria isolates from the commercial and laboratory fermented ogi showed that Lactobacillus sp, Leuconostoc sp and Citrobacter sp were present in all the samples, Micrococcus sp and Klebsiella sp were isolated from Eke- Okigwe and ABSU-up-gate markets varieties respectively, E. coli and Staphylococcus sp were present in Eke-Okigwe and Nkwo- Achara markets while Salmonella sp were isolated from the three markets. Hence, there are chances of contracting food borne diseases from commercially prepared ogi. Therefore, there is the need for sanitary measures in the production of fermented cereals so as to minimize the rate of food borne pathogens during processing and storage.

Keywords: Bacterial quality, fermentation, maize, Ogi.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

Abstract:

The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Alessandro A. Zizzari, Francesca Calabrese, Giovanni Indiveri, Andrea Coraddu, Diego Villa

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The aim of this paper is to present a comparative study on two different methods for the evaluation of the equilibrium point of a ship, core issue for designing an On Board Stability System (OBSS) module that, starting from geometry information of a ship hull, described by a discrete model in a standard format, and the distribution of all weights onboard calculates the ship floating conditions (in draught, heel and trim).

Keywords: Algorithms, Computer applications, Equilibrium, Marine applications, Stability System.

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Authors: Ime R. Udotong, Justina I. R. Udotong, Ofonime U. M. John

Abstract:

Brass terminal, one of the several crude oil and petroleum products storage/handling facilities in the Niger Delta was built in the 1980s. Activities at this site, over the years, released crude oil into this 3 m-deep, 1500 m-long canal lying adjacent to the terminal with oil floating on it and its sediment heavily polluted. To ensure effective clean-up, three major activities were planned: site characterization, bioremediation pilot plant construction and testing and full-scale bioremediation of contaminated sediment / bank soil by land farming. The canal was delineated into 12 lots and each characterized, with reference to the floating oily phase, contaminated sediment and canal bank soil. As a result of site characterization, a pilot plant for on-site bioremediation was designed and a treatment basin constructed for carrying out pilot bioremediation test. Following a designed sampling protocol, samples from this pilot plant were collected for analysis at two laboratories as a quality assurance / quality control check. Results showed that Brass Canal upstream is contaminated with dark, thick and viscous oily film with characteristic hydrocarbon smell while downstream, thin oily film interspersed with water was observed. Sediments were observed to be dark with mixture of brownish sandy soil with TPH ranging from 17,800 mg/kg in Lot 1 to 88,500 mg/kg in Lot 12 samples. Brass Canal bank soil was observed to be sandy from ground surface to 3m, below ground surface (bgs) it was silty-sandy and brownish while subsurface soil (4-10m bgs) was sandy-clayey and whitish/grayish with typical hydrocarbon smell. Preliminary results obtained so far have been very promising but were proprietary. This project is considered, to the best of technical literature knowledge, the first large-scale on-site bioremediation project in the Niger Delta region, Nigeria.

Keywords: Bioremediation, Contaminated sediment, Land farming, Oily sludge, Oil Terminal.

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Authors: N. Ravi Kumar, R. Kamalakannan

Abstract:

The inherent nature of normal boost converter has more voltage stress across the power electronics switch and ripple. The presented formation of the front end rectifier stage for a photovoltaic (PV) organization is mainly used to give the supply. Further increasing of the solar efficiency is achieved by connecting the zero voltage soft switching boost converter. The zero voltage boost converter is used to convert the low level DC voltage to high level DC voltage. The inherent nature of zero voltage switching boost converter is used to shrink the voltage tension across the power electronics switch and ripple. The input stage allows the determined power point tracking to be used to extract supreme power from the sun when it is available. The hardware setup was implemented by using PIC Micro controller (16F877A).

Keywords: Boost converter, duty cycle, hard switching, MOSFET, maximum power point tracking, photovoltaic, soft switching, zero voltage switching.

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Authors: Y. J. Huang, J. D. Yu, B. W. Hong, C. H. Tai, T. C. Kuo

Abstract:

In this paper, a multi-agent robot system is presented. The system consists of four robots. The developed robots are able to automatically enter and patrol a harmful environment, such as the building infected with virus or the factory with leaking hazardous gas. Further, every robot is able to perform obstacle avoidance and search for the victims. Several operation modes are designed: remote control, obstacle avoidance, automatic searching, and so on.

Keywords: autonomous robot, field programmable gate array, obstacle avoidance, ultrasonic sensor, wireless communication.

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Authors: Yngvar Berg, Omid Mirmotahari

Abstract:

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

Abstract:

Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: Fast vs slow BTI, Fast wafer level reliability, Negative bias temperature instability, NBTI measurement system, metal-oxide-semiconductor field-effect transistor, MOSFET, NBTI recovery, reliability.

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Authors: Shujaat A. Khan, Ghulam Murtaza

Abstract:

This presentation narrates the comparative analysis of the dissolution data nimesulide microparticles prepared with ethylcellulose, hydroxypropyl methylcellulose, chitosan and Poly(D,L-lactide-co-glycolide) as polymers. The analysis of release profiles showed that the variations noted in the release behavior of nimesulide from various microparticulate formulations are due to the nature of used polymer. In addition, maximum retardation in the nimesulide release was observed with HPMC (floating particles). Thus HPMC miacroparticles may be preferably employed for sustained release dosage form development.

Keywords: Nimesulide, microparticles, ethylcellulose, hydroxypropyl methylcellulose, chitosan and Poly(D, L-lactide-coglycolide).

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Authors: L. Ashok Kumar, N. Sujith Kumar

Abstract:

Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.

Keywords: Leakage current, common mode (CM), photovoltaic (PV) systems, pulse width modulation (PWM).

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Authors: Zdeňka Rendlová

Abstract:

This paper presents the mathematical description of the high-speed rotating system taking into account the influence of internal and external damping. The mathematical model is obtained by using the finite element method. The analyzed system is an automotive turbocharger understood as a rotor-bearing system. The circular cross-section shaft is equipped with one compressor wheel, one turbine wheel and is supported by two floating ring bearings. Based on the model, the dynamical analysis of a turbocharger is performed and stability conditions are evaluated.

Keywords: External damping, internal damping, journal bearing, stability, turbocharger.

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Authors: I Made Darmayuda, Zhou Jun, Krishna Mainali, Simon Ng Sheung Yan, Saisundar S, Eran Ofek

Abstract:

Personnel protection devices are cardinal in safety hazard applications. They are widely used in home, office and in industry environments to reduce the risk of lethal shock to human being and equipment safety. This paper briefly reviews various personnel protection devices also describes the basic working principle of conventional ground fault circuit interrupter (GFCI) or ground fault isolator (GFI), its disadvantages and ways to overcome the disadvantages with solid-state relay (SSR) based GFI with ultrafast response up on fault implemented in printed circuit board. This solid state GFI comprises discrete MOSFET based alternating current (AC) switches, linear optical amplifier, photovoltaic isolator and sense resistor. In conventional GFI, current transformer is employed as a sensing element to detect the difference in current flow between live and neutral conductor. If there is no fault in equipment powered through GFI, due to insulation failure of internal wires and windings of motors, both live and neutral currents will be equal in magnitude and opposite in phase.

Keywords: current transformer, electrocution, GFCI, GFI

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Authors: B. Rajesh Kamath, J. Sundara Rajan

Abstract:

Partial Discharge measurement is a very important means of assessing the integrity of insulation systems in a High Voltage apparatus. In compressed gas insulation systems, floating particles can initiate partial discharge activities which adversely affect the working of insulation. Partial Discharges below the inception voltage also plays a crucial in damaging the integrity of insulation over a period of time. This paper discusses the effect of loose and fixed Copper and Nichrome wire particles on the PD characteristics in SF6-N2 (10:90) gas mixtures at a pressure of 0.4MPa. The Partial Discharge statistical parameters and their correlation to the observed results are discussed.

Keywords: Gas Insulated transmission Line, Sulphur HexaFlouride, metallic Particles, Partial Discharge (PD), InceptionVoltage (Vi), Extinction Voltage (Ve), PD Statistical parameters.

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Authors: Jaouadi Ikram, Machhout Mohsen

Abstract:

The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process.

Keywords: QKD, BB84, protocol, cryptography, FPGA, key, security, communication.

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Authors: Li Yuan, Weizhu Wang, Kean Boon Lee, Haifeng Sun, Susai Lawrence Selvaraj, Shane Todd, Guo-Qiang Lo

Abstract:

In this work, the physical based device model of AlGaN/GaN high electron mobility transistors (HEMTs) has been established and the corresponding device operation behavior has been investigated also by using Sentaurus TCAD from Synopsys. Advanced AlGaN/GaN hetero-structures with GaN cap layer and AlN spacer have been considered and the GaN cap layer and AlN spacer are found taking important roles on the gate leakage blocking and off-state breakdown voltage enhancement.

Keywords: AlGaN/GaN, HEMT, Physical mechanism, TCAD simulation

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Authors: Kar Foo Chong, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

Keywords: CIC filter, decimation filter, half-band filter, lowpower.

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Authors: Tim Byrnes

Abstract:

Quantum computation using qubits made of two component Bose-Einstein condensates (BECs) is analyzed. We construct a general framework for quantum algorithms to be executed using the collective states of the BECs. The use of BECs allows for an increase of energy scales via bosonic enhancement, resulting in two qubit gate operations that can be performed at a time reduced by a factor of N, where N is the number of bosons per qubit. We illustrate the scheme by an application to Deutsch-s and Grover-s algorithms, and discuss possible experimental implementations. Decoherence effects are analyzed under both general conditions and for the experimental implementation proposed.

Keywords: Quantum, computing, information, Bose-Einstein condensates, macroscopic.

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Authors: M. Kovac

Abstract:

This article describes design of the 8-bit asynchronous microcontroller simulation model in VHDL. The model is created in ISE Foundation design tool and simulated in Modelsim tool. This model is a simple application example of asynchronous systems designed in synchronous design tools. The design process of creating asynchronous system with 4-phase bundled-data protocol and with matching delays is described in the article. The model is described in gate-level abstraction. The simulation waveform of the functional construction is the result of this article. Described construction covers only the simulation model. The next step would be creating synthesizable model to FPGA.

Keywords: Asynchronous, Microcontroller, VHDL, FPGA.

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Authors: Seung-Mok Han, Woo-Jin Nam, Seongsoo Lee

Abstract:

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from 4×4 to 16×16 blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a 16×16 block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

Keywords: HEVC, Core transform, Low area, Shift-and-add, PE reuse

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Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang

Abstract:

In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

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Authors: Haruo Shimada, Akinori Kanasugi

Abstract:

This paper proposes an architecture of dynamically reconfigurable arithmetic circuit. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operations. The proposed circuit is based on a complex number multiply-accumulation circuit which is used frequently in the field of digital signal processing. In addition, the proposed circuit performs real number double precision arithmetic operations. The data formats are single and double precision floating point number based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: arithmetic circuit, complex number, double precision, dynamic reconfiguration

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Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

Abstract:

This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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Authors: Dirk Hegemann, Martin Amberg

Abstract:

Sputter deposition processes, especially for sputtering from metal targets, are well investigated. For practical reasons, i.e. for industrial processes, energetic considerations for sputter deposition are useful in order to optimize the sputtering process. In particular, for substrates at floating conditions it is required to obtain energetic conditions during film growth that enables sufficient dense metal films of good quality. The influence of ion energies, energy density and momentum transfer is thus examined both for sputtering at the target as well as during film growth. Different regimes dominated by ion energy, energy density and momentum transfer were identified by using different plasma sources and by varying power input, pressure and bias voltage.

Keywords: Energy density, film growth, momentum transfer, sputtering.

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