Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 31097
64 bit Computer Architectures for Space Applications – A study

Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy


The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1948


[1] Cerruzi, P. A History of Modern Computing, 2nd Edition, MIT Press, May 2003.
[2] Nisan, N and Schocken, S. The Elements of Computing Systems, Building a Modern Computer from First Principles, MIT Press, June 2005.
[3] Hennessey, J.L. and Patterson, D.A. Computer Architecture - A Quantitative Approach, 4th Edition, Morgan Kaufman Publishers, 2007
[4] Hayes, J. P. Computer Architecture and Organization, 3rd Edition, McGraw-Hill, 1997.
[5] D. A. Patterson and J. L. Hennessey, "Computer Organization and Design - The Hardware/Software Interface", Elsevier Publications, South East Asia, 3rd Edition, 2005.
[6] C. Hamacher, Z. Vranesic and S. Zaky, "Computer Organization", 5th Edition, McGraw-Hill, 2002.
[7] A scientific study of the problems of digital engineering for space flight systems, NASA office of Logic Design, Dec 2004.
[8] J. Gaisler, "The LEON Processor User-s Manual", Version 2.3.7, Gaisler Research, August 2001.
[9] W. Wolf, "FPGA - Based System Design", Pearson Education Limited, First Indian Reprint, India, 2005.
[10] Dhir, A. The Digital Consumer Technology Handbook: A Comprehensive Guide to Devices, Standards, Future Directions, and Programmable Logic Solutions, Xilinx, Inc. 2005.
[11] BRASS - Berkeley Reconfigurable Architectures, Systems and Software :
[12] The SPARC Architecture Manual, Version 8, SAV080SI9308 SPARC International Inc., Menlo Park, CA 94025.
[13] The SPARC Architecture Manual, Version 9, SAV09R1459912 Prentice Hall, Englewood Cliffs, NJ 07632.
[14] Boney, Joel
[1992], "SPARC Version 9 Points the Way to the Next Generation RISC," SunWorld, October 1992, pp. 100-105
[15] Catanzaro, Ben, ed. The SPARC Technical Papers, Springer-Verlag, 1991.
[16] Cmelik, R. F., S. I. Kong, D. R. Ditzel, and E. J. Kelly, "An Analysis of MIPS and SPARC Instruction Set Utilization on the SPEC Benchmarks," Proceedings of the Fourth International Symposium on Architectural Support for Programming Languages and Operating Systems, April 8-11, 1991.
[17] Ditzel, David R.
[1993]. "SPARC Version 9: Adding 64 Bit Addressing and Robustness to an Existing RISC Architecture." Videotape available from University Video Communications, P. O. Box 5129, Stanford, CA, 94309
[18] Garner, R. B.
[1988]. "SPARC: The Scalable Processor Architecture," SunTechnology, vol. 1, no. 3, Summer, 1988; also appeared in M. Hall and J. Barry (eds.), The SunTechnology Papers, Springer-Verlag, 1990, pp. 75-99.
[19] OpenSPARC™ T1 Microarchitecture Specification, Sun Microsystems, Part No. 819-6650-10, August 2006, Revision A.
[20] ADSP-2106x SHARC® Processor User-s Manual, Revision 2.1, Part Number 82-000795-03, March 2004, Analog Devices, Inc., Norwood, Mass. 02062-9106.
[21] IEEE Standard for Binary Floating Point Arithmetic, IEEE Std 754- 1985, IEEE, New York, NY, 1985.
[22] IEEE Computer Society (1985), IEEE Standard for Binary Floating- Point Arithmetic, IEEE Standard 754-1985.
[23] Hollasch S, "IEEE Standard 754 Floating Point Numbers", Feb 2005
[25] "Wishbone Datasheet" revision B.3 -
[26] IEEE Standard 1149.1-1990: Standard Test Access Port and Boundary- Scan Architecture, 1990.
[27] Maunder, C.M. & R. Tulloss, Test Access Ports and Boundary Scan Architectures, IEEE Computer Society Press, 1991.
[28] Parker, Kenneth. The Boundary Scan Handbook, Kluwer Academic Press, 1992.
[29] Bleeker, Harry, P. van den Eijnden, & F. de Jong, Boundary-Scan TestÔÇö A Practical Approach, Kluwer Academic Press, 1993.
[30] Hewlett-Packard Co, "HP Boundary-Scan Tutorial and BSDL Reference Guide", Hewlett-Packard Part No. E1017-90001, 1992.
[31] Dr. Kris Kumar, Dr. K.N.B. Murthy, Niveditha Domse, , "64 bit Computer Architectures for Space Applications - A study", Research Project report submitted to ISRO as a part of RESPOND PROGRAM under Grant # 9/2/77/2006 jointly undertaken with ISRO and PES Institute of Technology, Bangalore, Nov 2007.