Commenced in January 2007
Paper Count: 31819
A Dynamically Reconfigurable Arithmetic Circuit for Complex Number and Double Precision Number
Abstract:This paper proposes an architecture of dynamically reconfigurable arithmetic circuit. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operations. The proposed circuit is based on a complex number multiply-accumulation circuit which is used frequently in the field of digital signal processing. In addition, the proposed circuit performs real number double precision arithmetic operations. The data formats are single and double precision floating point number based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1071678Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1402
 T. J. Todman, G. A. Constantinides, S. J. E. Wilton, O. Mencer, W. Luk and P. Y. K. Cheung, "Reconfigurable computing: architectures and design methods", IEE Proc.-Computers & Digital Techniques, vol. 152, no. 2, pp. 193 - 207, 2005.
 T. Sato, H. Watanabe, K. Shiba, "Implementation of dynamically reconfigurable processor DAPDNA-2", VLSI Design, Automation and Test, 2005 IEEE VLSI-TSA International Symposium, pp. 323-324, 2005.
 M J. Myjak, J. G. Delgado-Frias, "A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance", IEEE Trans. on VLSI Systems, vol.16, no.1, pp.14-23, Jan 2008.
 Monte Tull, et al., "High-Speed Complex Number Multiplier and Inner-Product Processor", IEEE Trans. on Circuits and Systems, vol. 3, pp.III-640 - III-643, Aug. 2002.
 Xilinx, Inc., ML401/ML402/ML403 Evaluation Platform User Guide UG080 (v2.5), May 2006
 Xilinx, Inc., MicroBlaze Processor Reference Guide UG081 (v9.0), 2008.