Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 26

Search results for: Leakage current

26 Design of a Hand-Held, Clamp-on, Leakage Current Sensor for High Voltage Direct Current Insulators

Authors: Morné Roman, Robert van Zyl, Nishanth Parus, Nishal Mahatho

Abstract:

Leakage current monitoring for high voltage transmission line insulators is of interest as a performance indicator. Presently, to the best of our knowledge, there is no commercially available, clamp-on type, non-intrusive device for measuring leakage current on energised high voltage direct current (HVDC) transmission line insulators. The South African power utility, Eskom, is investigating the development of such a hand-held sensor for two important applications; first, for continuous real-time condition monitoring of HVDC line insulators and, second, for use by live line workers to determine if it is safe to work on energised insulators. In this paper, a DC leakage current sensor based on magnetic field sensing techniques is developed. The magnetic field sensor used in the prototype can also detect alternating current up to 5 MHz. The DC leakage current prototype detects the magnetic field associated with the current flowing on the surface of the insulator. Preliminary HVDC leakage current measurements are performed on glass insulators. The results show that the prototype can accurately measure leakage current in the specified current range of 1-200 mA. The influence of external fields from the HVDC line itself on the leakage current measurements is mitigated through a differential magnetometer sensing technique. Thus, the developed sensor can perform measurements on in-service HVDC insulators. The research contributes to the body of knowledge by providing a sensor to measure leakage current on energised HVDC insulators non-intrusively. This sensor can also be used by live line workers to inform them whether or not it is safe to perform maintenance on energized insulators.

Keywords: Direct current, insulator, leakage current, live line, magnetic field, sensor, transmission lines.

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25 Modification of Electrical and Switching Characteristics of a Non Punch-Through Insulated Gate Bipolar Transistor by Gamma Irradiation

Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO2 interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center.

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24 Bipolar PWM and LCL Filter Configuration to Reduce Leakage Currents in Transformerless PV System Connected to Utility Grid

Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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23 Fabrication of High-Power AlGaN/GaN Schottky Barrier Diode with Field Plate Design

Authors: Chia-Jui Yu, Chien-Ju Chen, Jyun-Hao Liao, Chia-Ching Wu, Meng-Chyi Wu

Abstract:

In this letter, we demonstrate high-performance AlGaN/GaN planar Schottky barrier diodes (SBDs) on the silicon substrate with field plate structure for increasing breakdown voltage VB. A low turn-on resistance RON (3.55 mΩ-cm2), low reverse leakage current (< 0.1 µA) at -100 V, and high reverse breakdown voltage VB (> 1.1 kV) SBD has been fabricated. A virgin SBD exhibited a breakdown voltage (measured at 1 mA/mm) of 615 V, and with the field plate technology device exhibited a breakdown voltage (measured at 1 mA/mm) of 1525 V (the anode–cathode distance was LAC = 40 µm). Devices without the field plate design exhibit a Baliga’s figure of merit of VB2/ RON = 60.2 MW/cm2, whereas devices with the field plate design show a Baliga’s figure of merit of VB2/ RON = 340.9 MW/cm2 (the anode–cathode distance was LAC = 20 µm).

Keywords: AlGaN/GaN heterostructure, silicon substrate, Schottky barrier diode, high breakdown voltage, field plate, Baliga’s figure-of-merit.

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22 Reducing Test Vectors Count Using Fault Based Optimization Schemes in VLSI Testing

Authors: Vinod Kumar Khera, R. K. Sharma, A. K. Gupta

Abstract:

Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.

Keywords: Low power VLSI testing, independent fault, essential faults, test vector reduction.

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21 Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies

Authors: Zina Saheb, Ezz El-Masry

Abstract:

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.

Keywords: CMOS transistor, direct-tunneling current, floatinggate, gate-leakage current, simulation model.

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20 Seasonal Based Pollution Performance of 11kV and 33kV Silicon Composite Insulators

Authors: N. Sumathi, R. Srinivasa Rao

Abstract:

This paper presents the experimental results of 11 kV and 33 kV silicon composite insulators under artificial salt and urea polluted conditions. The tests were carried out under different seasons like summer, winter, and monsoon. The artificial pollution is prepared by properly dissolving the salt and urea in the water. The prepared salt and urea pollutions are sprayed on the insulators and dried up for sufficiently large time. The process is continued until a uniform layer is formed on the surface of insulator. For each insulator rating, four samples were tested. The maximum leakage current and breakdown voltage were measured. From experimental data, performance of test specimen is evaluated by comparing breakdown voltage and leakage current during different seasons when exposed to salt and urea polluted conditions. From these results the performance of the insulators can be predicted when they are installed in industrial, agricultural, and coastal areas. The experimental tests were carried out in the High Voltage laboratory using two stage cascade transformer having the rating of 1000 kVA, 500 kV.

Keywords: Silicon composite insulators, Urea pollution, Leakage current, Breakdown voltage, salt pollution, artificial pollution.

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19 A Double PWM Source Inverter Technique with Reduced Leakage Current for Application on Standalone Systems

Authors: Md. Noman Habib Khan, S. Khan, T. S. Gunawan, R. I. Boby

Abstract:

The photovoltaic (PV) panel with no galvanic isolation system is well known technique in the world which is effective and delivers power with enhanced efficiency. The PV generation presented here is for stand-alone system installed in remote areas when as the resulting power gets connected to electronic load installation instead of being tied to the grid. Though very small, even then transformer-less topology is shown to be with leakage in pico-ampere range. By using PWM technique PWM, leakage current in different situations is shown. The results shown in this paper show how the pico-ampere current is reduced to femto-ampere through use of inductors and capacitors of suitable values of inductor and capacitors with the load.

Keywords: Photovoltaic (PV) panel, Duty cycle, Pulse Duration Modulation (PDM), Leakage current.

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18 Design and Analysis of Highly Efficient and Reliable Single-Phase Transformerless Inverter for PV Systems

Authors: L. Ashok Kumar, N. Sujith Kumar

Abstract:

Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.

Keywords: Leakage current, common mode (CM), photovoltaic (PV) systems, pulse width modulation (PWM).

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17 Low Power CNFET SRAM Design

Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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16 Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High Speed Applications

Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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15 Low Leakage MUX/XOR Functions Using Symmetric and Asymmetric FinFETs

Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

Abstract:

In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

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14 Leakage Reduction ONOFIC Approach for Deep Submicron VLSI Circuits Design

Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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13 Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime

Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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12 Using LabVIEW Software in an Introductory Residual Current Device Course

Authors: B. Rajkumarsingh, S. Goolaup, A. Galleegadoo

Abstract:

Laboratory classes in Electrical Engineering are often hampered by safety issues, as students have to work on high voltage lines. One solution is to make use of virtual laboratory simulations, to help students understand the concepts taught in their coursework. In this context, we have conceived and implemented virtual lab experiments in connection with the study of earthing arrangements. In this work, software was developed, which aid student in understanding the working of a residual current device (RCD) in a TT earthing system. Various parameters, such as the earthing resistances, leakage currents and harmonics were included for a TT system with RCD connection.

Keywords: TT system, RCD, LabVIEW, Learning aids.

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11 Off-State Leakage Power Reduction by Automatic Monitoring and Control System

Authors: S. Abdollahi Pour, M. Saneei

Abstract:

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.

Keywords: leakage current, leakage power monitor, body biasing, low power

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10 A Novel Source/Drain-to-Gate Non-overlap MOSFET to Reduce Gate Leakage Current in Nano Regime

Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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9 Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method

Authors: F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, H. A. Elgomati, B. Y. Majlis, P. R. Apte

Abstract:

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Keywords: Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.

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8 A 16Kb 10T-SRAM with 4x Read-Power Reduction

Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu

Abstract:

This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

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7 Resistive RAM Based on Hfox and its Temperature Instability Study

Authors: Z. Fang, H.Y. Yu, W.J. Liu, N. Singh, G.Q. Lo

Abstract:

High performance Resistive Random Access Memory (RRAM) based on HfOx has been prepared and its temperature instability has been investigated in this work. With increasing temperature, it is found that: leakage current at high resistance state increases, which can be explained by the higher density of traps inside dielectrics (related to trap-assistant tunneling), leading to a smaller On/Off ratio; set and reset voltages decrease, which may be attributed to the higher oxygen ion mobility, in addition to the reduced potential barrier to create / recover oxygen ions (or oxygen vacancies); temperature impact on the RRAM retention degradation is more serious than electrical bias.

Keywords: RRAM, resistive switching, temperature instability.

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6 A Novel Nano-Scaled SRAM Cell

Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani

Abstract:

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

Keywords: SRAM Cell, leakage current, cell area.

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5 A Power-Gating Scheme to Reduce Leakage Power for P-type Adiabatic Logic Circuits

Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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4 Difference of Properties on Surface Leakage and Discharge Currents of Porcelain Insulator Material

Authors: Waluyo, Ngapuli I. Sinisuka, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of comparison between leakage currents and discharge currents. The leakage currents were obtained on polluted porcelain insulator. Whereas, the discharge currents were obtained on lightly artificial polluted porcelain specimen. The conducted measurements were leakage current or discharge current and applied voltage. The insulator or specimen was in a hermetically sealed chamber, and the current waveforms were analyzed using FFT. The result indicated that the leakage current (LC) on low RH condition the fifth harmonic would be visible, and followed by the seventh harmonic. The insulator had capacitive property. Otherwise, on 99% relative humidity, the fifth harmonic would also be visible, and the phase angle reached up to 12.2 degree. Whereas, on discharge current, the third harmonic would be visible, and followed by fifth harmonic. The third harmonic would increase as pressure reduced. On this condition, the specimen had a non-linear characteristics

Keywords: leakage current, discharge current, third harmonic, fifth harmonic, porcelain.

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3 Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics

Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

This paper presents a new compact analytical model of the gate leakage current in high-k based nano scale MOSFET by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semiempirical gate leakage current formulation in the BSIM 4 model. The gate tunneling currents have been calculated as a function of gate voltage for different gate dielectrics structures such as HfO2, Al2O3 and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The proposed model is compared and contrasted with santaurus simulation results to verify the accuracy of the model and excellent agreement is found between the analytical and simulated data. It is observed that proposed analytical model is suitable for different highk gate dielectrics simply by adjusting two fitting parameters. It was also shown that gate leakages reduced with the introduction of high-k gate dielectric in place of SiO2.

Keywords: Analytical model, High-k gate dielectrics, inelastic trap assisted tunneling, metal–oxide–semiconductor (MOS) devices.

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2 A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption

Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

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1 Study on Leakage Current Waveforms of Porcelain Insulator due to Various Artificial Pollutants

Authors: Waluyo, Parouli M. Pakpahan, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of leakage current waveforms which appears on porcelain insulator surface due to existence of artificial pollutants. The tests have been done using the chemical compounds of NaCl, Na2SiO3, H2SO4, CaO, Na2SO4, KCl, Al2SO4, MgSO4, FeCl3, and TiO2. The insulator surface was coated with those compounds and dried. Then, it was tested in the chamber where the high voltage was applied. Using correspondence analysis, the result indicated that the fundamental harmonic of leakage current was very close to the applied voltage and third harmonic leakage current was close to the yielded leakage current amplitude. The first harmonic power was correlated to first harmonic amplitude of leakage current, and third harmonic power was close to third harmonic one. The chemical compounds of H2SO4 and Na2SiO3 affected to the power factor of around 70%. Both are the most conductive, due to the power factor drastically increase among the chemical compounds.

Keywords: Chemical compound, harmonic, porcelain insulator, leakage current.

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