Search results for: K. N. Balasubramanya Murthy

Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

Abstract:

The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Donepudi Jagadish, Ravi Kumar Puli, K. Madhu Murthy

Abstract:

A zero dimensional model has been used to investigate the combustion performance of a single cylinder direct injection diesel engine fueled by biofuels with options like supercharging and exhaust gas recirculation. The numerical simulation was performed at constant speed. The indicated pressure, temperature diagrams are plotted and compared for different fuels. The emissions of soot and nitrous oxide are computed with phenomenological models. The experimental work was also carried out with biodiesel (palm stearin methyl ester) diesel blends, ethanol diesel blends to validate simulation results with experimental results, and observed that the present model is successful in predicting the engine performance with biofuels.

Keywords: Biofuels Zero Dimensional Modeling, EnginePerformance, Engine Emissions

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Authors: B. Prabhakara Rao, M. V. H. Bhaskara Murthy

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An Ad hoc wireless network comprises of mobile terminals linked and communicating with each other sans the aid of traditional infrastructure. Optimized Link State Protocol (OLSR) is a proactive routing protocol, in which routes are discovered/updated continuously so that they are available when needed. Hello messages generated by a node seeks information about its neighbor and if the latter fails to respond to a specified number of hello messages regulated by neighborhood hold time, the node is forced to assume that the neighbor is not in range. This paper proposes to evaluate OLSR routing protocol in a random mobility network having various neighborhood hold time intervals. The throughput and delivery ratio are also evaluated to learn about its efficiency for multimedia loads.

Keywords: Ad hoc Network, Optimized Link State Routing, Multimedia traffic

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Authors: Ch.V.Rama Rao, Gowthami., Harsha., Rajkumar., M.B.Rama Murthy, K.Srinivasa Rao, K.AnithaSheela

Abstract:

This paper presents a new method for estimating the nonstationary noise power spectral density given a noisy signal. The method is based on averaging the noisy speech power spectrum using time and frequency dependent smoothing factors. These factors are adjusted based on signal-presence probability in individual frequency bins. Signal presence is determined by computing the ratio of the noisy speech power spectrum to its local minimum, which is updated continuously by averaging past values of the noisy speech power spectra with a look-ahead factor. This method adapts very quickly to highly non-stationary noise environments. The proposed method achieves significant improvements over a system that uses voice activity detector (VAD) in noise estimation.

Keywords: Noise estimation, Non-stationary noise, Speechenhancement.

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Authors: Deepthi Narayan, Srikanta Murthy K., G. Hemantha Kumar

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Graph based image segmentation techniques are considered to be one of the most efficient segmentation techniques which are mainly used as time & space efficient methods for real time applications. How ever, there is need to focus on improving the quality of segmented images obtained from the earlier graph based methods. This paper proposes an improvement to the graph based image segmentation methods already described in the literature. We contribute to the existing method by proposing the use of a weighted Euclidean distance to calculate the edge weight which is the key element in building the graph. We also propose a slight modification of the segmentation method already described in the literature, which results in selection of more prominent edges in the graph. The experimental results show the improvement in the segmentation quality as compared to the methods that already exist, with a slight compromise in efficiency.

Keywords: Graph based image segmentation, threshold, Weighted Euclidean distance.

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Authors: G.V.K Murthy, S. Sivanagaraju, S. Satyanarayana, B. Hanumantha Rao

Abstract:

Distributed Generation (DG) systems are considered an integral part in future distribution system planning. Appropriate size and location of distributed generation plays a significant role in minimizing power losses in distribution systems. Among the benefits of distributed generation is the reduction in active power losses, which can improve the system performance, reliability and power quality. In this paper, Artificial Bee Colony (ABC) algorithm is proposed to determine the optimal DG-unit size and location by loss sensitivity index in order to minimize the real power loss, total harmonic distortion (THD) and voltage sag index improvement. Simulation study is conducted on 69-bus radial test system to verify the efficacy of the proposed method.

Keywords: Distributed generation, artificial bee colony method, loss reduction, radial distribution network.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

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The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Payal Abichandani, Rishi Prakash, Paras Nath Barwal, B. K. Murthy

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Information generated from various computerization processes is a potential rich source of knowledge for its designated community. To pass this information from generation to generation without modifying the meaning is a challenging activity. To preserve and archive the data for future generations it’s very essential to prove the authenticity of the data. It can be achieved by extracting the metadata from the data which can prove the authenticity and create trust on the archived data. Subsequent challenge is the technology obsolescence. Metadata extraction and standardization can be effectively used to resolve and tackle this problem. Metadata can be categorized at two levels i.e. Technical and Domain level broadly. Technical metadata will provide the information that can be used to understand and interpret the data record, but only this level of metadata isn’t sufficient to create trustworthiness. We have developed a tool which will extract and standardize the technical as well as domain level metadata. This paper is about the different features of the tool and how we have developed this.  

Keywords: Digital Preservation, Metadata, OAIS, PDI, XML.

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Authors: Nandini N., Srikanta Murthy K., G. Hemantha Kumar

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This paper includes two novel techniques for skew estimation of binary document images. These algorithms are based on connected component analysis and Hough transform. Both these methods focus on reducing the amount of input data provided to Hough transform. In the first method, referred as word centroid approach, the centroids of selected words are used for skew detection. In the second method, referred as dilate & thin approach, the selected characters are blocked and dilated to get word blocks and later thinning is applied. The final image fed to Hough transform has the thinned coordinates of word blocks in the image. The methods have been successful in reducing the computational complexity of Hough transform based skew estimation algorithms. Promising experimental results are also provided to prove the effectiveness of the proposed methods.

Keywords: Dilation, Document processing, Hough transform, Optical Character Recognition, Skew estimation, and Thinning.

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Authors: Usha N. Murthy, Rekha H. B., Mahaveer Devoor

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The introduction of more stringent pollution regulations, in relation to financial and social pressures for sustainable development, has pressed toward limiting the volumes of industrial and domestic effluents discharged into the environment - as well as to increase the efforts within research and development of new or more efficient wastewater treatment technologies. Considering both discharge volume and effluent composition, wastewater generated by the textile industry is rated as the most polluting among all industrial sectors. The pollution load is mainly due to spent dye baths, which are composed of unreacted dyes, dispersing agents, surfactants, salts and organics. In the present investigation, the textile dye wastewater was characterized by high color, chemical oxygen demand (COD), total dissolved solids (TDS) and pH. Electrochemical oxidation process for four plate electrodes was carried out at five different current intensities, out of which 0.14A has achieved maximum percentage removal of COD with 75% and 83% of color. The COD removal rate in kg COD/h/m² decreases with increase in the current intensity. The energy consumption increases with increase in the current intensity. Hence, textile dye wastewater can be effectively pretreated by electrochemical oxidation method where the process limits objectionable color while leaving the COD associated with organics left for natural degradation thus causing a sustainable reduction in pollution load.

Keywords: Electrochemical treatment, COD, color.

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Authors: B. Gopal, Pannala Krishna Murthy, G. N. Sreenivas

Abstract:

The increasing demand of electric power is giving an emphasis on the need for the maximum utilization of renewable energy sources. On the other hand maintaining power quality to satisfaction of utility is an essential requirement. In this paper the design aspects of a Unified Power Quality Conditioner integrated with photovoltaic system in a distributed generation is presented. The proposed system consist of series inverter, shunt inverter are connected back to back on the dc side and share a common dc-link capacitor with Distributed Generation through a boost converter. The primary task of UPQC is to minimize grid voltage and load current disturbances along with reactive and harmonic power compensation. In addition to primary tasks of UPQC, other functionalities such as compensation of voltage interruption and active power transfer to the load and grid in both islanding and interconnected mode have been addressed. The simulation model is design in MATLAB/ Simulation environment and the results are in good agreement with the published work.

Keywords: Distributed Generation(DG), Interconnected mode, Islanding mode, Maximum power point tracking (MPPT), Power Quality (PQ), Unified power quality conditioner (UPQC), Photovoltaic array (PV).

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Authors: G. Ramana Murthy, C. Senthilpari, P. Velrajkumar, Lim Tien Sze

Abstract:

In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.

Keywords: CSA Full Adder, Delay unit, IIR filter, Low-Power, PDP, Parametric Analysis, Propagation Delay, Throughput, VLSI.

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