Search results for: leakage power monitor

Authors: S. Abdollahi Pour, M. Saneei

Abstract:

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.

Keywords: leakage current, leakage power monitor, body biasing, low power

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Authors: Hong Li, Linfeng Li, Jianping Hu

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With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

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Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Waluyo, Parouli M. Pakpahan, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of leakage current waveforms which appears on porcelain insulator surface due to existence of artificial pollutants. The tests have been done using the chemical compounds of NaCl, Na2SiO3, H2SO4, CaO, Na2SO4, KCl, Al2SO4, MgSO4, FeCl3, and TiO2. The insulator surface was coated with those compounds and dried. Then, it was tested in the chamber where the high voltage was applied. Using correspondence analysis, the result indicated that the fundamental harmonic of leakage current was very close to the applied voltage and third harmonic leakage current was close to the yielded leakage current amplitude. The first harmonic power was correlated to first harmonic amplitude of leakage current, and third harmonic power was close to third harmonic one. The chemical compounds of H2SO4 and Na2SiO3 affected to the power factor of around 70%. Both are the most conductive, due to the power factor drastically increase among the chemical compounds.

Keywords: Chemical compound, harmonic, porcelain insulator, leakage current.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

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Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Md. Noman Habib Khan, S. Khan, T. S. Gunawan, R. I. Boby

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The photovoltaic (PV) panel with no galvanic isolation system is well known technique in the world which is effective and delivers power with enhanced efficiency. The PV generation presented here is for stand-alone system installed in remote areas when as the resulting power gets connected to electronic load installation instead of being tied to the grid. Though very small, even then transformer-less topology is shown to be with leakage in pico-ampere range. By using PWM technique PWM, leakage current in different situations is shown. The results shown in this paper show how the pico-ampere current is reduced to femto-ampere through use of inductors and capacitors of suitable values of inductor and capacitors with the load.

Keywords: Photovoltaic (PV) panel, Duty cycle, Pulse Duration Modulation (PDM), Leakage current.

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Authors: Anil S. Khopkar, Kartik S. Pandya

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Lightning overvoltage phenomenon in power systems cannot be avoided; however, it can be controlled to certain extent. To prevent system failure, power system equipment must be protected against overvoltage. Metal Oxide Surge Arrestors (MOSA) are connected in the system to provide protection against overvoltages. Under normal working conditions, MOSA function as, insulators, offering a conductive path during overvoltage events. MOSA consists of zinc oxide elements (ZnO Blocks) which has non-linear V-I characteristics. The ZnO blocks are connected in series and fitted in ceramic or polymer housing. Over time, these components degrade due to continuous operation. The degradation of zinc oxide elements increases the leakage current flowing through the surge arrestors. This increased leakage current results in elevated temperatures within the surge arrester, further decreasing the resistance of the zinc oxide elements. Consequently, the leakage current increases, leading to higher temperatures within the MOSA. This cycle creates thermal runaway conditions for the MOSA. Once a surge arrester reaches the thermal runaway condition, it cannot return to normal working conditions. This condition is a primary cause of premature failure of surge arrestors. Given that MOSA constitutes a core protective device for electrical power systems against transients, it contributes significantly to the reliable operation of power system networks. Therefore, periodic condition monitoring of surge arrestors is essential. Both online and offline condition monitoring techniques are available for surge arrestors. Offline condition monitoring techniques are not as popular because they require the removal of surge arrestors from the system, which requires system shutdown. Therefore, online condition monitoring techniques are more commonly used. This paper presents an evaluation technique for the surge arrester condition based on leakage current analysis. The maximum amplitudes of total leakage current (IT), fundamental resistive leakage current (IR), and third harmonic resistive leakage current (I3rd) are analyzed as indicators for surge arrester condition monitoring.

Keywords: Metal Oxide Surge Arrester, MOSA, Over voltage, total leakage current, resistive leakage current, third harmonic resistive leakage current, capacitive leakage current.

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

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CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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Authors: Antonio Carlos Marques Alvim, Fernando Carvalho da Silva, Aquilino Senra Martinez

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For a quick and accurate calculation of spatial neutron distribution in nuclear power reactors 3D nodal codes are usually used aiming at solving the neutron diffusion equation for a given reactor core geometry and material composition. These codes use a second order polynomial to represent the transverse leakage term. In this work, a nodal method based on the well known nodal expansion method (NEM), developed at COPPE, making use of this polynomial expansion was modified to treat the transverse leakage term for the external surfaces of peripheral reflector nodes. The proposed method was implemented into a computational system which, besides solving the diffusion equation, also solves the burnup equations governing the gradual changes in material compositions of the core due to fuel depletion. Results confirm the effectiveness of this modified treatment of peripheral nodes for practical purposes in PWR reactors.

Keywords: Transverse leakage, nodal expansion method, power density, PWR reactors

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Authors: Morné Roman, Robert van Zyl, Nishanth Parus, Nishal Mahatho

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Leakage current monitoring for high voltage transmission line insulators is of interest as a performance indicator. Presently, to the best of our knowledge, there is no commercially available, clamp-on type, non-intrusive device for measuring leakage current on energised high voltage direct current (HVDC) transmission line insulators. The South African power utility, Eskom, is investigating the development of such a hand-held sensor for two important applications; first, for continuous real-time condition monitoring of HVDC line insulators and, second, for use by live line workers to determine if it is safe to work on energised insulators. In this paper, a DC leakage current sensor based on magnetic field sensing techniques is developed. The magnetic field sensor used in the prototype can also detect alternating current up to 5 MHz. The DC leakage current prototype detects the magnetic field associated with the current flowing on the surface of the insulator. Preliminary HVDC leakage current measurements are performed on glass insulators. The results show that the prototype can accurately measure leakage current in the specified current range of 1-200 mA. The influence of external fields from the HVDC line itself on the leakage current measurements is mitigated through a differential magnetometer sensing technique. Thus, the developed sensor can perform measurements on in-service HVDC insulators. The research contributes to the body of knowledge by providing a sensor to measure leakage current on energised HVDC insulators non-intrusively. This sensor can also be used by live line workers to inform them whether or not it is safe to perform maintenance on energized insulators.

Keywords: Direct current, insulator, leakage current, live line, magnetic field, sensor, transmission lines.

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Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-V_t transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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Authors: W. S. Hsu, Y. Chiang, H. C. Chen, J. R. Wang, S. W. Chen, J. H. Yang, C. Shih

Abstract:

Not only radiation materials, but also the normal chemical material stored in the power plant can cause a risk to the residents. In this research, the ALOHA code was used to perform the concentration analysis under the CO₂ storage burst or leakage conditions for Kuosheng nuclear power plant (NPP). The Final Safety Analysis Report (FSAR) and data were used in this study. Additionally, the analysis results of ALOHA code were compared with the R.G. 1.78 failure criteria in order to confirm the control room habitability. The comparison results show that the ALOHA result for burst case was 0.923 g/m³ which was below the criteria. However, the ALOHA results for leakage case was 11.3 g/m³.

Keywords: BWR, ALOHA, habitability, Kuosheng.

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Authors: Ki-Tae Park, Young-Joon Yu, Chin-Hyung Lee, Woosang Lee

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Recently, as the scale of construction projects has increases, more ground excavation for foundations is carried out than ever before. Consequently, damage to underground ducts (gas, water/sewage or oil pipelines, communication cables or power cable ducts) or superannuated pipelines frequently cause serious accidents resulting in damage to life and property. (In Korea, the total length of city water pipelines was approximately 2,000 km as of the end of 2009.) In addition, large amounts of damage caused by fractures, water and gas leakage caused by superannuation or damage to underground ducts in construction has been reported. Therefore, a system is required to precisely detect defects and deterioration in underground pipelines and the locations of such defects, for timely and accurate maintenance or replacement of the ducts. In this study, a system was developed which can locate underground structures (gas and water pipelines, power cable ducts, etc.) in 3D-coordinates and monitor the degree and position of defects using an Inertial Measurement Unit (IMU) sensing technique. The system can prevent damage to underground ducts and superannuated pipelines during construction, and provide reliable data for maintenance. The utility of the IMU sensing technique used in aircraft and ships in civil applications was verified.

Keywords: IMU, Pipelines, 3D-Coordinate, monitor.

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Authors: Waluyo, Ngapuli I. Sinisuka, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of comparison between leakage currents and discharge currents. The leakage currents were obtained on polluted porcelain insulator. Whereas, the discharge currents were obtained on lightly artificial polluted porcelain specimen. The conducted measurements were leakage current or discharge current and applied voltage. The insulator or specimen was in a hermetically sealed chamber, and the current waveforms were analyzed using FFT. The result indicated that the leakage current (LC) on low RH condition the fifth harmonic would be visible, and followed by the seventh harmonic. The insulator had capacitive property. Otherwise, on 99% relative humidity, the fifth harmonic would also be visible, and the phase angle reached up to 12.2 degree. Whereas, on discharge current, the third harmonic would be visible, and followed by fifth harmonic. The third harmonic would increase as pressure reduced. On this condition, the specimen had a non-linear characteristics

Keywords: leakage current, discharge current, third harmonic, fifth harmonic, porcelain.

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Authors: Toshihiko Sasama, Takao Kawamura, Kazunori Sugahara

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Nowadays, new home appliances and office appliances have been developed that communicate with users through the Internet, for remote monitor and remote control. However, developments and sales of these new appliances are just started, then, many products in our houses and offices do not have these useful functions. In few years, we add these new functions to the outlet, it means multifunctional electrical power socket plug adapter. The outlet measure power consumption of connecting appliances, and it can switch power supply to connecting appliances, too. Using this outlet, power supply of old appliances can be control and monitor. And we developed the interface system using web browser to operate it from users[1]. But, this system need to set up LAN cables between outlets and so on. It is not convenience that cables around rooms. In this paper, we develop the system that use wireless mobile ad hoc network instead of wired LAN to communicate with the outlets.

Keywords: outlet, remote monitor, mobile ad hoc network, zigbee.

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Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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Authors: Vinod Kumar Khera, R. K. Sharma, A. K. Gupta

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Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.

Keywords: Low power VLSI testing, independent fault, essential faults, test vector reduction.

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Authors: W. R. Li, J. K. Xia, R. Q. Peng, Z. Y. Guo, L. Jiang

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According to 3D magnetic circuit of the transverse flux PM linear machine, distribution law is presented, and analytical expression of axial end flux leakage is derived using numerical method. Maxwell stress tensor is used to solve detent force of mover. A 3D finite element model of the transverse flux PM machine is built to analyze the flux distribution and detent force. Experimental results of the prototype verified the validity of axial end flux leakage and detent force theoretical derivation, the research on axial end flux leakage and detent force provides a valuable reference to other types of linear machine.

Keywords: Transverse flux PM linear machine, flux distribution, axial end flux leakage, detent force.

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Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

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In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

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Authors: Mohammad Taghi Shervani Tabar, Zahra Poursharifi

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The interaction of the blade tip with the casing boundary layer and the leakage flow may lead to a kind of cavitation namely tip vortex cavitation. In this study, the onset of tip vortex cavitation was experimentally investigated in an axial flow pump. For a constant speed and a fixed angle of attack and by changing the flow rate, the pump head, input power, output power and efficiency were calculated and the pump characteristic curves were obtained. The cavitation phenomenon was observed with a camera and a stroboscope. Finally, the critical flow region, which tip vortex cavitation might have occurred, was identified. The results show that just by adjusting the flow rate, out of the specified region, the possibility of occurring tip vortex cavitation, decreases to a great extent.

Keywords: Axial flow pump, Gap cavitation, Leakage vortex, Tip vortex cavitation.

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Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu

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This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

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Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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Authors: S.M.Hosseinalipour, H.Aghakhani

Abstract:

Considering the numerous applications of the study of the flow due to leakage in a buried pipe in unsaturated porous media, finding a proper model to explain the influence of the effective factors is of great importance.There are various important factors involved in this type of flow such as: pipe leakage size and location, burial depth, the degree of the saturation of the surrounding porous medium, characteristics of the porous medium, fluid type and pressure of the upstream.In this study, the flow through unsaturated porous media due to leakage of a buried pipe for up and down leakage location is studied experimentally and numerically and their results are compared. Study results show that Darcy equation together with BCM method (for calculating the relative permeability) have suitable ability for predicting the flow due to leakage of buried pipes in unsaturated porous media.

Keywords: Buried, Leaking pipe, Porous media, Unsaturated

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Authors: Somaye Abdollahi Pour, Mohsen Saneei

Abstract:

This paper describes a novel monitoring scheme to minimize total active power in digital circuits depend on the demand frequency, by adjusting automatically both supply voltage and threshold voltages based on circuit operating conditions such as temperature, process variations, and desirable frequency. The delay monitoring results, will be control and apply so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. Design details of power monitor are examined using simulation framework in 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 40 μW for 32nm technology; moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop. This design provides up to 40% reduction in power consumption in active mode.

Keywords: active mode, delay monitor, body biasing, VDD scaling, low power.

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Authors: Mahmoud Huleihil

Abstract:

In this study, the performance of a thermodynamic gas cycle of magnetohydrodynamic (MHD) power generation is considered and presented in terms of power efficiency curves. The dissipation mechanisms considered include: fluid friction modeled by means of the isentropic efficiency of the compressor, heat transfer leakage directly from the hot reservoir to the cold heat reservoir, and constant velocity of the MHD generator. The study demonstrates that power and efficiency vanish at the extremes of both slow and fast operating conditions. These points are demonstrated on power efficiency curves and the locus of efficiency at maximum power and the locus of maximum efficiency. Qualitatively, the considered loss mechanisms have a similar effect on the efficiency at maximum power operation and on maximum efficiency operation, thus these efficiencies are reduced, even for small values of the loss mechanisms.

Keywords: Magnetohydrodynamic generator, electrical efficiency, maximum power, maximum efficiency, heat engine.

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

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Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani

Abstract:

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

Keywords: SRAM Cell, leakage current, cell area.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

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In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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Authors: Javier Barbaran, Manuel Dıaz, Inaki Esteve, Bartolome Rubio

Abstract:

Wireless Sensor Networks (WSNs) have attracted the attention of many researchers. This has resulted in their rapid integration in very different areas such as precision agriculture,environmental monitoring, object and event detection and military surveillance. Due to the current WSN characteristics this technology is specifically useful in industrial areas where security, reliability and autonomy are basic, such as nuclear power plants, chemical plants, and others. In this paper we present a system based on WSNs to monitor environmental conditions around and inside a nuclear power plant, specifically, radiation levels. Sensor nodes, equipped with radiation sensors, are deployed in fixed positions throughout the plant. In addition, plant staff are also equipped with mobile devices with higher capabilities than sensors such as for example PDAs able to monitor radiation levels and other conditions around them. The system enables communication between PDAs, which form a Mobile Ad-hoc Wireless Network (MANET), and allows workers to monitor remote conditions in the plant. It is particularly useful during stoppage periods for inspection or in the event of an accident to prevent risk situations.

Keywords: MANETs, Mobile computing, Radiation monitoring, Wireless Sensor Networks.

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Authors: Liping Zhang, Kelin Li

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In this paper, a class of impulsive BAM fuzzy cellular neural networks with time delays in the leakage terms is formulated and investigated. By establishing a delay differential inequality and M-matrix theory, some sufficient conditions ensuring the existence, uniqueness and global exponential stability of equilibrium point for impulsive BAM fuzzy cellular neural networks with time delays in the leakage terms are obtained. In particular, a precise estimate of the exponential convergence rate is also provided, which depends on system parameters and impulsive perturbation intention. It is believed that these results are significant and useful for the design and applications of BAM fuzzy cellular neural networks. An example is given to show the effectiveness of the results obtained here.

Keywords: Global exponential stability, bidirectional associative memory, fuzzy cellular neural networks, leakage delays, impulses.

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