%0 Journal Article
	%A Pardeep Singh and  Sanjay Sharma and  Parvinder S. Sandhu
	%D 2011
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 49, 2011
	%T A 16Kb 10T-SRAM with 4x Read-Power Reduction
	%U https://publications.waset.org/pdf/12643
	%V 49
	%X This work aims to reduce the read power consumption
as well as to enhance the stability of the SRAM cell during the read
operation. A new 10-transisor cell is proposed with a new read
scheme to minimize the power consumption within the memory core.
It has separate read and write ports, thus cell read stability is
significantly improved. A 16Kb SRAM macro operating at 1V
supply voltage is demonstrated in 65 nm CMOS process. Its read
power consumption is reduced to 24% of the conventional design.
The new cell also has lower leakage current due to its special bit-line
pre-charge scheme. As a result, it is suitable for low-power mobile
applications where power supply is restricted by the battery.
	%P 97 - 101