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A 16Kb 10T-SRAM with 4x Read-Power Reduction

Authors: Pardeep Singh, Sanjay Sharma, Parvinder S. Sandhu


This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords: A 16Kb 10T-SRAM, 4x Read-Power Reduction

Digital Object Identifier (DOI):

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[1] S. K. Jain and P. Agarwal, "A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology," in VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on, 2006, p. 4
[2] E. Grossar, "Technolgy-aware design of SRAM memory circuits," in Departement of Electronic. Vol. PhD Leuven: Katholieke Universiteit 2007, p. 226.
[3] F. Frustaci, P. Corsonello, S. Perri, and G. Cocorullo, "Leakage energy reduction techniques in deep submicron cache memories: a comparative study," in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, p. 4 pp.
[4] L. Zhiyu and V. Kursun, "Characterization of a Novel Nine-Transistor SRAM Cell," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, pp. 488-492, 2008.
[5] S. A. Tawfik and V. Kursun, "Dynamic wordline voltage swing for low leakage and stable static memory banks," in Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, 2008, pp. 1894-1897.
[6] K. Itoh, "Low-voltage limitations and challenges of nano-scale CMOS VLSIs-A personal view of memory designer,"in Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT2008. IEEE International Conference on, 2008, pp.177-180.
[7] A. Vladimirescu, C. Yu, O. Thomas, Q. Huifang, D. Markovic, A.Valentian, R. Ionita, J. Rabaey, and A. Amara, "Ultra-low-voltage robust design issues in deep-submicron CMOS," in Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on, 2004, pp. 49-52.
[8] B. H. Calhoun and A. Chandrakasan, "Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS," in Solid-State Circuits Conference, 2005 ESSCIRC 2005. Proceedings of the 31st European,2005, pp. 363-366.
[9] E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," Solid-State Circuits, IEEE Journal of, vol. 22, pp.748-754, 1987.
[10] W. Dong, P. Li, and G. M. Huang, "SRAM dynamic stability: Theory,variability and analysis," in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 378- 385.
[11] D. E. Khalil, M. Khellah, K. Nam-Sung, Y. Ismail, T. Karnik, and V.K. De, "Accurate Estimation of SRAM Dynamic Stability," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, pp.1639-1647, 2008.
[12] A. Seshadri and T. W. Houston, "The dynamic stability of a 10T SRAM compared to 6T SRAMs at the 32nm node using an accelerated Monte Carlo technique," in Circuits and Systems Workshop: Systemon-Chip - Design, Applications, Integration, and Software, 2008 IEEE Dallas, 2008, pp. 1-4.
[13] C. C. Wang, C. L. Lee, and W. J. Lin, "A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme," Circuits and Systems I:Regular Papers, IEEE Transactions on, vol. 54, pp. 1069-1076, 2007.