Leakage Reduction ONOFIC Approach for Deep Submicron VLSI Circuits Design

Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1336316

References:

[1] H. Wong and H. Iwai, "On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors”, Microelectronic Engineering, Vol. 83 (10), pp. 1867-1904, 2006.
[2] S.G. Narendra, "Challenges and design choices in nanoscale CMOS,” ACM Journal on Emerging Technologies in Computing Systems, vol. 1 (1), pp. 7-49, 2005.
[3] K. Haghdad and M. Anis, "Design-specific optimization considering supply and threshold voltage variations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27 (10), pp. 1891-1901, 2008.
[4] S. Borkar, "Design challenges of technology scaling”, IEEE Micro, Vol. 19 (4), pp. 23-29, 1999.
[5] S. Dhar, M. Pattanaik and P. Rajaram, "Advancement in nanoscale CMOS device design en route to ultra-low-power applications”, VLSI Design, Vol. 2011, Art. No. 178516, 2011.
[6] J. Xue, T. Li, Y. Deng and Z. Yu, "Full-chip leakage analysis for 65 nm CMOS technology and beyond”, Integration, the VLSI Journal, Vol. 43 (4), pp. 353-364, 2010.
[7] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS”, IEEE Journal of Solid-State Circuits, Vol. 30 (8), pp. 847-854, 1995.
[8] S. Narendra, S. Borkar, V. De, D. Antoniadis and A. Chandrakasan, "Scaling of Stack Effect and its Application for Leakage Reduction”, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, pp. 195-200, 2001.
[9] H. Kawaguchi, K. Nose and T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Pico-ampere Stand-By Current”, IEEE Journal of Solid State Circuits, Vol. 35 (10), pp. 1498-1501, 2000.
[10] J.C. Park and V.J. Mooney III, "Sleepy Stack Leakage Reduction”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14 (11), pp. 1250-1263, 2006.
[11] N. Hanchate and N. Ranganathan, "LECTOR: a technique for leakage reduction in CMOS circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12 (2), pp. 196-205, 2004.
[12] S. Katrue and D. Kudithipudi, "GALEOR: Leakage reduction for CMOS circuits”, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), pp. 574-577, 2008.
[13] P. Lakshmikanthan and A. Nuñez, "VCLEARIT: A VLSI CMOS Circuit Leakage Reduction Technique for Nanoscale Technologies”, ACM SIGARCH Computer Architecture News, Vol. 35 (5), pp. 10-16, 2007.
[14] S. Mukhopadhyay, C. Neau, R.T. Cakici, A. Agarwal, C.H. Kim and K. Roy, "Gate Leakage Reduction for Scaled Devices Using Transistor Stacking”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11 (4), pp. 716-730, 2003.
[15] S. Goel, M.A. Elgamel, M.A. Bayoumi and Y. Hanafy, "Design methodologies for high-performance noise-tolerant XOR-XNOR circuits”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 53 (4), pp. 867-878, 2006.