**Commenced**in January 2007

**Frequency:**Monthly

**Edition:**International

**Paper Count:**30843

##### A Power-Gating Scheme to Reduce Leakage Power for P-type Adiabatic Logic Circuits

**Authors:**
Hong Li,
Jianping Hu,
Linfeng Li

**Abstract:**

**Keywords:**
low power,
Leakage reduction,
deep submicronCMOS circuits,
P-type adiabatic circuits

**Digital Object Identifier (DOI):**
doi.org/10.5281/zenodo.1334247

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[9] Dong Zhou, Jianping Hu, and Huiying Dong, "An energy-efficient power-gating adiabatic circuits using transmission gate switches," IEEE International Conference on ASIC (AICON 2007), Guilin, China, 2007, pp. 145-148.

[10] F. Hamzaoglu and M. R. Stan, "Circuit-level techniques to control gate leakage for sub-100nm CMOS, " Int. Symp on Low Power Electronics and Design, 2002, pp. 60 - 63.

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