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A Power-Gating Scheme to Reduce Leakage Power for P-type Adiabatic Logic Circuits

Authors: Hong Li, Linfeng Li, Jianping Hu


With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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[1] N. S. Kim, T. Austin, J. S. Hu, and M. Jane, "Leakage current: Moore-s law meets static power," Computer, vol. 38, no. 12, 2003, pp. 68-75.
[2] F. Fallah and M. Pedram, " Standby and active leakage current control and minimization in CMOS VLSI circuits," IEICE Transactions on Electronics, vol. E88-C, no. 4, 2005, pp. 509-519.
[3] A. Abdullah, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," IEEE Trans Very Large Scale Integration (VLSI), vol. 12, no. 2, 2004, pp. 40-154.
[4] A. B. Kahng, "Design challenges at 65nm and beyond," Proceedings of the Conference on Design, Automation and Test in Europe, Nice, France, 2007, pp. 1466-1467.
[5] K. K. Kim, Y. B. Kim, M. Choi, and N. Park, "Leakage minimization technique for nanoscale CMOS VLSI," IEEE Design and Test of Computers, vol. 24, no. 4, Aug. 2007, pp. 322-330.
[6] Y. Moon and D. K. Jeong, "An efficient charge recovery logic circuit", IEEE J.of Solid-State Circuits, vol.31, no. 4, 1996, pp.514-522.
[7] Hu, Jianping, Li, Hong, Dong, Huiying, "A low-power adiabatic register file with two types of energy-efficient line drivers", IEEE International Midwest Symposium on Circuits and Systems, 2005, pp. 1753-1756.
[8] P. Teichmann, J. Fischer, and S. Henzler, et al, "Power-clock gating in adiabatic logic circuits, " in Proc. PATMOS-05, 2005, pp. 638-646.
[9] Dong Zhou, Jianping Hu, and Huiying Dong, "An energy-efficient power-gating adiabatic circuits using transmission gate switches," IEEE International Conference on ASIC (AICON 2007), Guilin, China, 2007, pp. 145-148.
[10] F. Hamzaoglu and M. R. Stan, "Circuit-level techniques to control gate leakage for sub-100nm CMOS, " Int. Symp on Low Power Electronics and Design, 2002, pp. 60 - 63.
[11] Wei Zhao and Yu Cao, "New generation of predictive technology model for Sub-45nm design exploration," Department of Electrical Engineering, Arizona State University, 2006.
[12] A. Kramer, J. S. Denker, B. Flower, J. Moroney, "2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits," International Symposium on Low Power Design, Dana Point, April 1995, pp. 191-196.
[13] F. Liu, and K. T. Lau, "Pass-transistor adiabatic logic with NMOS pull-down configuration," Electronics Letters, vol. 34, no. 8, 1998, pp. 739-741.
[14] Jianping Hu, Tiefeng Xu, Junjun Yu, and Yinshui Xia, "Low power dual transmission gate adiabatic logic circuits and design of SRAM," IEEE International Midwest Symposium on Circuits and Systems, Hiroshima, Japan, July 2004, pp.565-568.
[15] D. Maksimovic and V. G. Oklobdzija, "Integrated power clock generators for low energy logic," IEEE Power Electronics Specialists Conf., Atlanta, GA, 1995, pp.61-67.