%0 Journal Article %A Pejman Hosseiniun and Rose Shayeghi and Iman Rahbari and Mohamad Reza Kalhor %D 2014 %J International Journal of Electrical and Computer Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 92, 2014 %T Low Power CNFET SRAM Design %U https://publications.waset.org/pdf/9998924 %V 92 %X CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase. %P 1245 - 1248