Low Leakage MUX/XOR Functions Using Symmetric and Asymmetric FinFETs

Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

Abstract:

In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1078825

References:

[1] S.Cayouette, "Static Power Dissipation in Arithmetic Circuits: The Nanometer Domain", Royal Military Collage Of Canada, 2007.
[2] Ajay N.Bhoj, Niraj K.Jha,"Design of ultra-low-leakage logic gates and Flip-flops in High-performance FinFET Technology",Quality Electron Design, IEEE 12th international Symposium, 2011.
[3] Matteo Agostinelli, Massimo Alioto, David Esseni, and Luca selmi, "Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis with Bulk Technology", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol.18, No. 2, 2010.
[4] J.G.Fossum, "UFDG MOSFET MODEL (Linux Ver.3.71)", SOI Group, University of Florida Gainesville, FL 32611-6130, 2010.
[5] Massimo Alioto, "Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET standard cells", IEEE Transaction On Very Large Scale Integeration(VLSI) Systems, vol.19, No. 5, 2010.
[6] S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design. MC Graw Hill, 2003.
[7] M. Wang, "Independent-Gate FinFET Circuit Design Methodology ," IAENG International Journal of Computer Science,Vol. 37,No. 1, 2010.
[8] M. Wang, "Low Power, Area Efficient FinFET Circuit Design ," The World Congress on Engineering and Computer Science, 2009.