@article{(Open Science Index):https://publications.waset.org/pdf/9998924,
	  title     = {Low Power CNFET SRAM Design},
	  author    = {Pejman Hosseiniun and  Rose Shayeghi and  Iman Rahbari and  Mohamad Reza Kalhor},
	  country	= {},
	  institution	= {},
	  abstract     = {CNFET has emerged as an alternative material to
silicon for high performance, high stability and low power SRAM
design in recent years. SRAM functions as cache memory in
computers and many portable devices. In this paper, a new SRAM
cell design based on CNFET technology is proposed. The proposed
SRAM cell design for CNFET is compared with SRAM cell designs
implemented with the conventional CMOS and FinFET in terms of
speed, power consumption, stability, and leakage current. The
HSPICE simulation and analysis show that the dynamic power
consumption of the proposed 8T CNFET SRAM cell’s is reduced
about 48% and the SNM is widened up to 56% compared to the
conventional CMOS SRAM structure at the expense of 2% leakage
power and 3% write delay increase.
},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {8},
	  number    = {8},
	  year      = {2014},
	  pages     = {1245 - 1248},
	  ee        = {https://publications.waset.org/pdf/9998924},
	  url   	= {https://publications.waset.org/vol/92},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 92, 2014},
	}