Reducing Test Vectors Count Using Fault Based Optimization Schemes in VLSI Testing

Authors: Vinod Kumar Khera, R. K. Sharma, A. K. Gupta

Abstract:

Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.

Keywords: Low power VLSI testing, independent fault, essential faults, test vector reduction.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1339530

References:

[1] "International Technology Road Map for Semiconductors," 2013.
[2] Hnatek, E.R., "IC Quality – Where Are We," in Proceedings of the IEEE International Test Conference, pp. 430–445, 1987.
[3] Report, "International Sematech, The International Technology Roadmap for semiconductors (ITRS)," 2001.
[4] Chandra, "Reduction of SOC Test Data Volume, Scan Power and testing time using Alternate run-length Codes," in ACM/IEEE Design Automation Conference (DAC), 2002.
[5] Athas, "Low power digital systems based on adiabatic-switching principles," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 398-416, 1994.
[6] M. Abramovici, Digital System Testing and Testable Design, Piscataway- New Jersey: IEEE Press, 1994.
[7] C.S. Lin, "Test Compaction for combinational Circuits," IEEE Transactions on CAD, vol. 14, no. 11, pp. 1370-1378, 1995.
[8] B.C. Rosales, "Test Generation and Dynamic Compaction of Tests," in International Test Conference, 1979.
[9] M.H. Schulz, "Socrates: A highly Efficient Automatic Test Pattern Generation Scheme," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 126-137, 1988.
[10] S.B. Akers, "On the Role of Independent Fault Sets in the Generation of Minimal Test Sets," in International Test Conference, 1987.
[11] Pomeranz, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," IEEE Transactions on CAD, vol. 12, no. 7, pp. 1040-1049, 1993.
[12] S.Kundu. et.al, "A Novel, Technique to reduce both leakage and peak power during scan testing," in IEEE Region 10 and Third International Conference on Industrial and Information Systems, 2008.
[13] S. K. et.al, "Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing," INTEGRATION, the VLSI Journal, vol. 45, pp. 211-221, 2012.
[14] A. El-Maleh, "Test Vector Decomposition based static compaction based static compaction algorithms for combinational circuits," IET Computer Digit, vol. 1, no. 4, pp. 364-368, 2007.
[15] B. Krishnamurthy, "Test Counting: A tool for VLSI Testing," IEEE Design & Test of Computers, vol. 6, no. 5, pp. 58-77, 1989.
[16] Z. Navabi, Digital System Test and Testable Design using HDL Models and Architectures, London: Springer, 2011.
[17] S. Kajihara, "XID: Don't care Identification for Test Patterns for combinational Circuits," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, 2004.
[18] V.D. Agrawal, "Diagnostic and Detection of fault collapsing for multiple output circuits," in Design, Automation and Test (DATE), Europe, 2005.
[19] H.DSHA, "Atalanta: An Efficient ATPG for Combinational Circuits," Virginia Poly. Institute and State University, Virginia, 1993.
[20] Al-Suwaiyan, "An efficient test Relaxation Technique for combinational and full-scan sequential circuits," in VLSI Test Symposium, Monterey, CA, 2002.
[21] G.Tromp, "Minimal Test Sets for combinational Circuits," in International Test Conference, 1991.
[22] Hamzaoglu, I.; Patel, J.H., "Test set compaction algorithms for combinational circuits," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.19, no.8, pp.957-963, Aug 2000