Search results for: Short Circuit Power

Authors: Sajid Iqbal, Masood Ahmed, Suhail Aftab Qureshi

Abstract:

DC-DC converters are widely used in regulated switched mode power supplies and in DC motor drive applications. There are several sources of unwanted nonlinearity in practical power converters. In addition, their operation is characterized by switching that gives birth to a variety of nonlinear dynamics. DC-DC buck and boost converters controlled by pulse-width modulation (PWM) have been simulated. The voltage waveforms and attractors obtained from the circuit simulation have been studied. With the onset of instability, the phenomenon of subharmonic oscillations, quasi-periodicity, bifurcations, and chaos have been observed. This paper is mainly motivated by potential contributions of chaos theory in the design, analysis and control of power converters, in particular and power electronics circuits, in general.

Keywords: Buck converter, boost converter, period- doubling, chaos, bifurcation, strange attractor.

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Authors: Qingjiang Li, Hui Xu, Haijun Liu, Xiaobo Tian

Abstract:

To judge whether the memristor can be interpreted as the fourth fundamental circuit element, we propose a variable-relation criterion of fundamental circuit elements. According to the criterion, we investigate the nature of three fundamental circuit elements and the memristor. From the perspective of variables relation, the memristor builds a direct relation between the voltage across it and the current through it, instead of a direct relation between the magnetic flux and the charge. Thus, it is better to characterize the memristor and the resistor as two special cases of the same fundamental circuit element, which is the memristive system in Chua-s new framework. Finally, the definition of memristor is refined according to the difference between the magnetic flux and the flux linkage.

Keywords: Memristor, Fundamental, Variable-Relation Criterion, Memristive system

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Authors: P. Ram Mohan, M. Vijaya Kumar, O. V. Raghava Reddy

Abstract:

This paper deals with the simulation of a Boost Power Factor Correction (PFC) Converter with Electro Magnetic Interference (EMI) Filter. The diode rectifier with output capacitor gives poor power factor. The Boost Converter of PFC Circuit is analyzed and then simulated with diode rectifier. The Boost PFC Converter with EMI Filter is simulated for resistive load. The power factor is improved using the proposed converter.

Keywords: Boost Converter, Power Factor Correction, Electro Magnetic Interference, Diode Rectifier

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Authors: J. Mohan, S. Maheshwari

Abstract:

A new circuit topology realizing a first-order currentmode all-pass filter is proposed using two dual-output second generation current conveyor and two passive components. The circuit possesses low-input and high-output impedance, which makes it ideal for current-mode systems. The proposed circuit is verified through PSPICE simulation results.

Keywords: active filter, all-pass filter, current-mode, current conveyor.

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Authors: Chang-le Lu, Yong Chen

Abstract:

The shortest path question is in a graph theory model question, and it is applied in many fields. The most short-path question may divide into two kinds: Single sources most short-path, all apexes to most short-path. This article mainly introduces the problem of all apexes to most short-path, and gives a new parallel algorithm of all apexes to most short-path according to the Dijkstra algorithm. At last this paper realizes the parallel algorithms in the technology of C # multithreading.

Keywords: Dijkstra algorithm, parallel algorithms, multi-thread technology, most short-path, ratio.

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Authors: P. V. V. Rama Rao, B. Kali Prasanna, Y. T. R. Palleswari

Abstract:

Renewable energy is derived from natural processes that are replenished constantly. Included in the definition is electricity and heat generated from solar, wind, ocean, hydropower, biomass, geothermal resources, and bio-fuels and hydrogen derived from renewable resources. Each of these sources has unique characteristics which influence how and where they are used. This paper presents the modeling the simulation of solar and hydro hybrid energy sources in MATLAB/SIMULINK environment. It simulates all quantities of Hybrid Electrical Power system (HEPS) such as AC output current of the inverter that injected to the load/grid, load current, grid current. It also simulates power output from PV and Hydraulic Turbine Generator (HTG), power delivered to or from grid and finally power factor of the inverter for PV, HTG and grid. The proposed circuit uses instantaneous p-q (real-imaginary) power theory.

Keywords: Photovoltaic Array, Hydraulic Turbine Generator, Electrical Utility (EU), Hybrid Electrical Power Supply.

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Authors: Chenguang Guo, Lei Chen, Yanlong Zhang

Abstract:

This paper describes a novel optimized JTAG interface circuit between a JTAG controller and target IC. Being able to access JTAG using only one or two pins, this circuit does not change the original boundary scanning test frequency of target IC. Compared with the traditional JTAG interface which based on IEEE std. 1149.1, this reduced pin technology is more applicability in pin limited devices, and it is easier to control the scale of target IC for the designer.

Keywords: Boundary scan, JTAG interface, Test frequency, Reduced pin

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Authors: Sun-Ki Hong, Yong-Ho Cho, Ki-Seok Kim, Tae-Sam Kang

Abstract:

Piezoelectric actuator is treated as RC load when it is modeled electrically. For some piezoelectric actuator applications, arbitrary voltage is required to actuate. Especially for unidirectional arbitrary voltage driving like as sine wave, some special inverter with circuit that can charge and discharge the capacitive energy can be used. In this case, the difference between power supply level and the object voltage level for RC load is varied. Because the control gain is constant, the controlled output is not uniform according to the voltage difference. In this paper, for charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator, the controller gain is controlled according to the voltage difference. With the proposed simple idea, the load voltage can have controlled smoothly although the voltage difference is varied. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: Analog voltage inverter, Capacitive load, Gain control, DC-DC converter, Piezoelectric, Voltage waveform.

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Authors: Aakash Subramanian, Vansh Pal Singh Makh, Abhijit Mitra

Abstract:

A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.

Keywords: Asynchronous Communication, Digital Detector, Combinational logic output, Sampling clock generator, Hardwareimplementation.

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Authors: M. Nirmala

Abstract:

Power quality in terms of power factor, THD and precisely regulated output voltage are the major key factors for efficient operation of power electronic converters. This paper presents an easy and effective active wave shaping control scheme for the pulsed input current drawn by the uncontrolled diode bridge rectifier thereby achieving power factor nearer to unity and also satisfying the THD specifications. It also regulates the output DC-bus voltage. CCM boost power factor correction with constant frequency operation features smaller inductor current ripple resulting in low RMS currents on inductor and switch thus leading to low electromagnetic interference. The objective of this work is to develop an active PFC control circuit using CCM boost converter implementing variable duty cycle control. The proposed scheme eliminates inductor current sensing requirements yet offering good performance and satisfactory results for maintaining the power quality. Simulation results have been presented which covers load changes also.

Keywords: CCM Boost converter, Power factor Correction, Total harmonic distortion, Variable Duty Cycle.

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Authors: Neeraj K. Chasta

Abstract:

This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.

Keywords: Current Mode, Comparator, High Resolution, High Speed.

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Authors: Sidhartha Panda, Narayana Prasad Padhy

Abstract:

With constraints on data availability and for study of power system stability it is adequate to model the synchronous generator with field circuit and one equivalent damper on q-axis known as the model 1.1. This paper presents a systematic procedure for modelling and simulation of a single-machine infinite-bus power system installed with a thyristor controlled series compensator (TCSC) where the synchronous generator is represented by model 1.1, so that impact of TCSC on power system stability can be more reasonably evaluated. The model of the example power system is developed using MATLAB/SIMULINK which can be can be used for teaching the power system stability phenomena, and also for research works especially to develop generator controllers using advanced technologies. Further, the parameters of the TCSC controller are optimized using genetic algorithm. The non-linear simulation results are presented to validate the effectiveness of the proposed approach.

Keywords: Genetic algorithm, MATLAB/SIMULINK, modelling and simulation, power system stability, single-machineinfinite-bus power system, thyristor controlled series compensator.

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Authors: P. Selvam, S. Senthil Kumar

Abstract:

Maximum Power Point Tracking (MPPT) has played a vital role to enhance the efficiency of solar photovoltaic (PV) power generation under varying atmospheric temperature and solar irradiation. However, it is hard to track the maximum power point using conventional linear controllers due to the natural inheritance of nonlinear I-V and P-V characteristics of solar PV systems. Fuzzy Logic Controller (FLC) is suitable for nonlinear system control applications and eliminating oscillations, circuit complexities present in the conventional perturb and observation and incremental conductance methods respectively. Hence, in this paper, FLC is proposed for tracking exact MPPT of solar PV power generation system under varying solar irradiation conditions. The effectiveness of the proposed FLC-based MPPT controller is validated through simulation and analysis using MATLAB/Simulink.

Keywords: Fuzzy logic controller, maximum power point tracking, photovoltaic.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Ioannis Binas, Marios Moschakis

Abstract:

Electrical faults in transmission and distribution networks can have great impact on the electrical equipment used. Fault effects depend on the characteristics of the fault as well as the network itself. It is important to anticipate the network’s behavior during faults when planning a new equipment installation, as well as troubleshooting. Moreover, working backwards, we could be able to estimate the characteristics of the fault when checking the perceived effects. Different transformer winding connections dominantly used in the Greek power transfer and distribution networks and the effects of 1-phase to neutral, phase-to-phase, 2-phases to neutral and 3-phase faults on different locations of the network were simulated in order to present voltage sag characteristics. The study was performed on a generic network with three steps down transformers on two voltage level buses (one 150 kV/20 kV transformer and two 20 kV/0.4 kV). We found that during faults, there are significant changes both on voltage magnitudes and on phase angles. The simulations and short-circuit analysis were performed using the PSCAD simulation package. This paper presents voltage characteristics calculated for the simulated network, with different approaches on the transformer winding connections during symmetrical and asymmetrical faults on various locations.

Keywords: Phase angle shift, power quality, transformer winding connections, voltage sag propagation.

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Authors: Mohammad Javad Dehghani

Abstract:

In the power quality analysis non-stationary nature of voltage distortions require some precise and powerful analytical techniques. The time-frequency representation (TFR) provides a powerful method for identification of the non-stationary of the signals. This paper investigates a comparative study on two techniques for analysis and visualization of voltage distortions with time-varying amplitudes. The techniques include the Discrete Wavelet Transform (DWT), and the S-Transform. Several power quality problems are analyzed using both the discrete wavelet transform and S–transform, showing clearly the advantage of the S– transform in detecting, localizing, and classifying the power quality problems.

Keywords: Power quality, S-Transform, Short Time FourierTransform , Wavelet Transform, instantaneous sag, swell.

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Authors: P. Chaipanya, R. Keawchai, W. Sombatsanongkhun, S. Jantaramporn

Abstract:

To manage the demand of wireless communication that has been dramatically increased, switched beam antenna in smart antenna system is focused. Implementation of switched beam antennas at mobile terminals such as notebook or mobile handset is a preferable choice to increase the performance of the wireless communication systems. This paper proposes the low complexity switched beam antenna using single element of antenna which is suitable to implement at mobile terminal. Main beam direction is switched by changing the positions of short circuit on the radiating patch. There are four cases of switching that provide four different directions of main beam. Moreover, the performance in terms of Signal to Interference Ratio when utilizing the proposed antenna is compared with the one using omni-directional antenna to confirm the performance improvable.

Keywords: Switched beam, shorted circuit, single element, signal to interference ratio.

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Yue-Der Lin, Ya-Hsueh Chien, Yen-Ting Lin, Shih-Fan Wang, Cheng-Lun Tsai, Ching-Che Tsai

Abstract:

Capacitive electrocardiogram (ECG) measurement is an attractive approach for long-term health monitoring. However, there is little literature available on its implementation, especially for multichannel system in standard ECG leads. This paper begins from the design criteria for capacitive ECG measurement and presents a multichannel limb-lead capacitive ECG system with conductive fabric tapes pasted on a double layer PCB as the capacitive sensors. The proposed prototype system incorporates a capacitive driven-body (CDB) circuit to reduce the common-mode power-line interference (PLI). The presented prototype system has been verified to be stable by theoretic analysis and practical long-term experiments. The signal quality is competitive to that acquired by commercial ECG machines. The feasible size and distance of capacitive sensor have also been evaluated by a series of tests. From the test results, it is suggested to be greater than 60 cm2 in sensor size and be smaller than 1.5 mm in distance for capacitive ECG measurement.

Keywords: capacitive driven-body (CDB) circuit, capacitive electrocardiogram (ECG) measurement, capacitive sensor, conductive fabric tape, power-line interference (PLI).

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Authors: Charline David, Alexandre Blondin Massé, Arnaud Zinflou

Abstract:

We present a multiple equation time series approach for the short-term load forecasting applied to the electrical power load consumption for the whole Quebec province, in Canada. More precisely, we take into account three meteorological variables — temperature, cloudiness and wind speed —, and we use meteorological measurements taken at different locations on the territory. Our final model shows an average MAPE score of 1.79% over an 8-years dataset.

Keywords: Short-term load forecasting, special days, time series, multiple equations, parallelization, clustering.

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Authors: Muhammad Mujtaba Asad, Razali Bin Hassan, Fahad Sherwani

Abstract:

This paper explains about the voltage output for DC to DC boost converter between open loop, PID controller and fuzzy logic controller through Matlab Simulink. Simulink input voltage was set at 12V and the voltage reference was set at 24V. The analysis on the deviation of voltage resulted that the difference between reference voltage setting and the output voltage is always lower. Comparison between open loop, PID and FLC shows that, the open loop circuit having a bit higher on the deviation of voltage. The PID circuit boosts for FLC has a lesser deviation of voltage and proved that it is such a better performance on control the deviation of voltage during the boost mode.

Keywords: Boost Convertors, Power Electronics, PID, Fuzzy logic, Open loop.

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Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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Authors: Yukinari Minagi , Akinori Kanasugi

Abstract:

This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: dynamic reconfiguration, floating-point arithmetic, double precision, FPGA

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Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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Authors: Hari Babu Kotte, Radhika Ambatipudi, Dr. Kent Bertilsson

Abstract:

The experimental and theoretical results of a ZVS (Zero Voltage Switching) isolated flyback DC-DC converter using multilayered coreless PCB step down 2:1 transformer are presented. The performance characteristics of the transformer are shown which are useful for the parameters extraction. The measured energy efficiency of the transformer is found to be more than 94% with the sinusoidal input voltage excitation. The designed flyback converter has been tested successfully upto the output power level of 10W, with a switching frequency in the range of 2.7MHz-4.3MHz. The input voltage of the converter is varied from 25V-40V DC. Frequency modulation technique is employed by maintaining constant off time to regulate the output voltage of the converter. The energy efficiency of the isolated flyback converter circuit under ZVS condition in the MHz frequency region is found to be approximately in the range of 72-84%. This paper gives the comparative results in terms of the energy efficiency of the hard switched and soft switched flyback converter in the MHz frequency region.

Keywords: Coreless PCB step down transformer, DC-DCconverter, Flyback, Hard Switched Converter, MHz frequencyregion, Multilayered PCB transformer, Zero Voltage Switching

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Authors: Gianluca Cornetta, David J. Santos, Balwant Godara

Abstract:

A 1.2 V, 0.61 mA bias current, low noise amplifier (LNA) suitable for low-power applications in the 2.4 GHz band is presented. Circuit has been implemented, laid out and simulated using a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB power gain a noise figure NF< 2.28 dB and a 1-dB compression point of -15.69 dBm, while dissipating 0.74 mW. Such performance make this design suitable for wireless sensor networks applications such as ZigBee.

Keywords: Current Reuse, IEEE 802.15.4 (ZigBee), Low NoiseAmplifiers, Wireless Sensor Networks.

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Authors: Mayank Shakya, Soundra Pandian. K. K

Abstract:

A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.

Keywords: Linear Feedback Shift Register, Total Hamming Distance, Fault Coverage, Control Logic

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Authors: M. L. Akinyemi, T. J. Abodurin, A. O. Boyo, J. A. O. Olugbuyiro

Abstract:

Organic dyes from Cola acuminata (C. acuminata), Lupinus arboreus (L. arboreus) and Bougainvillea spectabilis (B. spectabilis) leaves and their mixtures were used as sensitizers to manufacture dye-sensitized solar cells (DSSC). Photoelectric measurements of C. acuminata showed a short circuit current (J_sc) of 0.027 mA/ cm², 0.026 mA/ cm² and 0.018 mA/ cm² with a mixture of mercury chloride and iodine (Hgcl₂ + I); potassium bromide and iodine (KBr + I); and potassium chloride and iodine (KCl + I) respectively. The open circuit voltage (V_oc) was 24 mV, 25 mV and 20 mV for the three dyes respectively. L. arboreus had J_sc of 0.034 mA/ cm², 0.021 mA/ cm² and 0.013 mA/ cm²; and corresponding V_oc of 28 mV, 14.2 mV and 15 mV for the three electrolytes respectively. B. spectabilis recorded J_sc 0.023 mA/ cm², 0.026 mA/ cm² and 0.015 mA/ cm²; and corresponding V_oc values of 6.2 mV, 14.3 mV and 4.0 mV for the three electrolytes respectively. It was observed that the fill factor (FF) was 0.140 for C. acuminata, 0.3198 for L. arboreus and 0.1138 for B. spectabilis. Internal conversions of 0.096%, 0.056% and 0.063% were recorded for three dyes when combined with (KBr + I) electrolyte. The internal efficiency of C. acuminata DSSC was highest in value.

Keywords: Dye-sensitized Solar Cells, Organic dye, C. acuminate, L. arboreus, B. spectabilis, Dye Mixture.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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