Commenced in January 2007
Paper Count: 31824
A Power Reduction Technique for Built-In-Self Testing Using Modified Linear Feedback Shift Register
Abstract:A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1062648Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1882
 Seongmoon Wang, Sandeep K.Gupta, "ATPG for HEAT Dissipation Minimization During Test Application" IEEE Trans. On computer Vol: 47, No. 2, 1998, pp. 256-262.
 Abu-Issa, A.S., Quigley, S.F., "Bit Swapping LFSR for low-power BIST", vol.44, Issue 6,401-402,2008.
 Mayank Shakya, Soundra Pandian K.K. "Low Power Testing of CMOS Circuits: A Review", proc. of NCSCV-09,vl 106, 2009.
 Walter Aloisi and Rosario Mita, Member, IEEE, Gated clock design of Linear Feedback Shift Register , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSÔÇöII: EXPRESS BRIEFS, VOL. 55, NO. 6, JUNE 2008. references).
 P.Girard, C.landrault, S.Pravossoudovitch, D Severac, "Reducing Test power Consumption During Test Vector Ordering" IEEE International Symposium on Circuits and Systems, 1998.
 M. Bellos, D. Bakalis, D.Nikolos, X. Kavousianos, "Low Power Testing by vector Ordering with Vector Repetition", pp 205- 210,2004.
 Artem Sokolov, Alodeep Sanyal, Darrell Whitley, Yashwant Malaiya, "Dynamic Power Minimization During Combinational Circuit Testing as a Traveling Salesman Problem", pp. 1088-1095,2005.
 Anshuman Chandra, Kishendu Chakrabarty, "Low Power Scan Testing and Test Data Compression for a System on Chip", IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, Vol.21, No.5, May 2002.
 K.Paramasivam, K.Gunavathi,"Reordering Algorithm for Minimizing Test Power in VLSI Circuits", Engineering Letter, Issues_v14, February 2007.