Yukinari Minagi and Akinori Kanasugi
A Processor with Dynamically Reconfigurable Circuit for FloatingPoint Arithmetic
1269 - 1273
2010
4
8
International Journal of Electronics and Communication Engineering
https://publications.waset.org/pdf/13110
https://publications.waset.org/vol/44
World Academy of Science, Engineering and Technology
This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in generalpurpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floatingpoint arithmetic which is
frequently used in science and technology. The data format is
floatingpoint based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Open Science Index 44, 2010