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A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic

Authors: Yukinari Minagi , Akinori Kanasugi


This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.

Keywords: FPGA, Dynamic Reconfiguration, double precision, floating-point arithmetic

Digital Object Identifier (DOI):

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