@article{(Open Science Index):https://publications.waset.org/pdf/10012360,
	  title     = {A Low Power and High-Speed Conditional-Precharge Sense Amplifier Based Flip-Flop Using Single Ended Latch},
	  author    = {Guo-Ming Sung and  Naga Raju Naik R.},
	  country	= {},
	  institution	= {},
	  abstract     = {Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {16},
	  number    = {1},
	  year      = {2022},
	  pages     = {1 - 5},
	  ee        = {https://publications.waset.org/pdf/10012360},
	  url   	= {https://publications.waset.org/vol/181},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 181, 2022},
	}