Search results for: leakage current

Authors: Waluyo, Ngapuli I. Sinisuka, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of comparison between leakage currents and discharge currents. The leakage currents were obtained on polluted porcelain insulator. Whereas, the discharge currents were obtained on lightly artificial polluted porcelain specimen. The conducted measurements were leakage current or discharge current and applied voltage. The insulator or specimen was in a hermetically sealed chamber, and the current waveforms were analyzed using FFT. The result indicated that the leakage current (LC) on low RH condition the fifth harmonic would be visible, and followed by the seventh harmonic. The insulator had capacitive property. Otherwise, on 99% relative humidity, the fifth harmonic would also be visible, and the phase angle reached up to 12.2 degree. Whereas, on discharge current, the third harmonic would be visible, and followed by fifth harmonic. The third harmonic would increase as pressure reduced. On this condition, the specimen had a non-linear characteristics

Keywords: leakage current, discharge current, third harmonic, fifth harmonic, porcelain.

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Authors: Waluyo, Parouli M. Pakpahan, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of leakage current waveforms which appears on porcelain insulator surface due to existence of artificial pollutants. The tests have been done using the chemical compounds of NaCl, Na2SiO3, H2SO4, CaO, Na2SO4, KCl, Al2SO4, MgSO4, FeCl3, and TiO2. The insulator surface was coated with those compounds and dried. Then, it was tested in the chamber where the high voltage was applied. Using correspondence analysis, the result indicated that the fundamental harmonic of leakage current was very close to the applied voltage and third harmonic leakage current was close to the yielded leakage current amplitude. The first harmonic power was correlated to first harmonic amplitude of leakage current, and third harmonic power was close to third harmonic one. The chemical compounds of H2SO4 and Na2SiO3 affected to the power factor of around 70%. Both are the most conductive, due to the power factor drastically increase among the chemical compounds.

Keywords: Chemical compound, harmonic, porcelain insulator, leakage current.

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Authors: Morné Roman, Robert van Zyl, Nishanth Parus, Nishal Mahatho

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Leakage current monitoring for high voltage transmission line insulators is of interest as a performance indicator. Presently, to the best of our knowledge, there is no commercially available, clamp-on type, non-intrusive device for measuring leakage current on energised high voltage direct current (HVDC) transmission line insulators. The South African power utility, Eskom, is investigating the development of such a hand-held sensor for two important applications; first, for continuous real-time condition monitoring of HVDC line insulators and, second, for use by live line workers to determine if it is safe to work on energised insulators. In this paper, a DC leakage current sensor based on magnetic field sensing techniques is developed. The magnetic field sensor used in the prototype can also detect alternating current up to 5 MHz. The DC leakage current prototype detects the magnetic field associated with the current flowing on the surface of the insulator. Preliminary HVDC leakage current measurements are performed on glass insulators. The results show that the prototype can accurately measure leakage current in the specified current range of 1-200 mA. The influence of external fields from the HVDC line itself on the leakage current measurements is mitigated through a differential magnetometer sensing technique. Thus, the developed sensor can perform measurements on in-service HVDC insulators. The research contributes to the body of knowledge by providing a sensor to measure leakage current on energised HVDC insulators non-intrusively. This sensor can also be used by live line workers to inform them whether or not it is safe to perform maintenance on energized insulators.

Keywords: Direct current, insulator, leakage current, live line, magnetic field, sensor, transmission lines.

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Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

Abstract:

In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

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Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Md. Noman Habib Khan, S. Khan, T. S. Gunawan, R. I. Boby

Abstract:

The photovoltaic (PV) panel with no galvanic isolation system is well known technique in the world which is effective and delivers power with enhanced efficiency. The PV generation presented here is for stand-alone system installed in remote areas when as the resulting power gets connected to electronic load installation instead of being tied to the grid. Though very small, even then transformer-less topology is shown to be with leakage in pico-ampere range. By using PWM technique PWM, leakage current in different situations is shown. The results shown in this paper show how the pico-ampere current is reduced to femto-ampere through use of inductors and capacitors of suitable values of inductor and capacitors with the load.

Keywords: Photovoltaic (PV) panel, Duty cycle, Pulse Duration Modulation (PDM), Leakage current.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani

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To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

Keywords: SRAM Cell, leakage current, cell area.

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Authors: Anil S. Khopkar, Kartik S. Pandya

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Lightning overvoltage phenomenon in power systems cannot be avoided; however, it can be controlled to certain extent. To prevent system failure, power system equipment must be protected against overvoltage. Metal Oxide Surge Arrestors (MOSA) are connected in the system to provide protection against overvoltages. Under normal working conditions, MOSA function as, insulators, offering a conductive path during overvoltage events. MOSA consists of zinc oxide elements (ZnO Blocks) which has non-linear V-I characteristics. The ZnO blocks are connected in series and fitted in ceramic or polymer housing. Over time, these components degrade due to continuous operation. The degradation of zinc oxide elements increases the leakage current flowing through the surge arrestors. This increased leakage current results in elevated temperatures within the surge arrester, further decreasing the resistance of the zinc oxide elements. Consequently, the leakage current increases, leading to higher temperatures within the MOSA. This cycle creates thermal runaway conditions for the MOSA. Once a surge arrester reaches the thermal runaway condition, it cannot return to normal working conditions. This condition is a primary cause of premature failure of surge arrestors. Given that MOSA constitutes a core protective device for electrical power systems against transients, it contributes significantly to the reliable operation of power system networks. Therefore, periodic condition monitoring of surge arrestors is essential. Both online and offline condition monitoring techniques are available for surge arrestors. Offline condition monitoring techniques are not as popular because they require the removal of surge arrestors from the system, which requires system shutdown. Therefore, online condition monitoring techniques are more commonly used. This paper presents an evaluation technique for the surge arrester condition based on leakage current analysis. The maximum amplitudes of total leakage current (IT), fundamental resistive leakage current (IR), and third harmonic resistive leakage current (I3rd) are analyzed as indicators for surge arrester condition monitoring.

Keywords: Metal Oxide Surge Arrester, MOSA, Over voltage, total leakage current, resistive leakage current, third harmonic resistive leakage current, capacitive leakage current.

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Authors: S. Abdollahi Pour, M. Saneei

Abstract:

This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead of proposed circuit in terms of its power consumption is about 10 μW for 32nm technology and about 12 μW for 65nm technology at the same power supply voltage as the core power supply. Moreover the results show that our proposed circuit design is not far sensitive to the temperature variations and also process variations. Besides, uses the simple blocks which offer good sensitivity, high speed, the continuously feedback loop.

Keywords: leakage current, leakage power monitor, body biasing, low power

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Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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Authors: Zina Saheb, Ezz El-Masry

Abstract:

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.

Keywords: CMOS transistor, direct-tunneling current, floatinggate, gate-leakage current, simulation model.

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-V_t transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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Authors: W. R. Li, J. K. Xia, R. Q. Peng, Z. Y. Guo, L. Jiang

Abstract:

According to 3D magnetic circuit of the transverse flux PM linear machine, distribution law is presented, and analytical expression of axial end flux leakage is derived using numerical method. Maxwell stress tensor is used to solve detent force of mover. A 3D finite element model of the transverse flux PM machine is built to analyze the flux distribution and detent force. Experimental results of the prototype verified the validity of axial end flux leakage and detent force theoretical derivation, the research on axial end flux leakage and detent force provides a valuable reference to other types of linear machine.

Keywords: Transverse flux PM linear machine, flux distribution, axial end flux leakage, detent force.

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Authors: N. Sumathi, R. Srinivasa Rao

Abstract:

This paper presents the experimental results of 11 kV and 33 kV silicon composite insulators under artificial salt and urea polluted conditions. The tests were carried out under different seasons like summer, winter, and monsoon. The artificial pollution is prepared by properly dissolving the salt and urea in the water. The prepared salt and urea pollutions are sprayed on the insulators and dried up for sufficiently large time. The process is continued until a uniform layer is formed on the surface of insulator. For each insulator rating, four samples were tested. The maximum leakage current and breakdown voltage were measured. From experimental data, performance of test specimen is evaluated by comparing breakdown voltage and leakage current during different seasons when exposed to salt and urea polluted conditions. From these results the performance of the insulators can be predicted when they are installed in industrial, agricultural, and coastal areas. The experimental tests were carried out in the High Voltage laboratory using two stage cascade transformer having the rating of 1000 kVA, 500 kV.

Keywords: Silicon composite insulators, Urea pollution, Leakage current, Breakdown voltage, salt pollution, artificial pollution.

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Authors: S.M.Hosseinalipour, H.Aghakhani

Abstract:

Considering the numerous applications of the study of the flow due to leakage in a buried pipe in unsaturated porous media, finding a proper model to explain the influence of the effective factors is of great importance.There are various important factors involved in this type of flow such as: pipe leakage size and location, burial depth, the degree of the saturation of the surrounding porous medium, characteristics of the porous medium, fluid type and pressure of the upstream.In this study, the flow through unsaturated porous media due to leakage of a buried pipe for up and down leakage location is studied experimentally and numerically and their results are compared. Study results show that Darcy equation together with BCM method (for calculating the relative permeability) have suitable ability for predicting the flow due to leakage of buried pipes in unsaturated porous media.

Keywords: Buried, Leaking pipe, Porous media, Unsaturated

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Authors: Liping Zhang, Kelin Li

Abstract:

In this paper, a class of impulsive BAM fuzzy cellular neural networks with time delays in the leakage terms is formulated and investigated. By establishing a delay differential inequality and M-matrix theory, some sufficient conditions ensuring the existence, uniqueness and global exponential stability of equilibrium point for impulsive BAM fuzzy cellular neural networks with time delays in the leakage terms are obtained. In particular, a precise estimate of the exponential convergence rate is also provided, which depends on system parameters and impulsive perturbation intention. It is believed that these results are significant and useful for the design and applications of BAM fuzzy cellular neural networks. An example is given to show the effectiveness of the results obtained here.

Keywords: Global exponential stability, bidirectional associative memory, fuzzy cellular neural networks, leakage delays, impulses.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

This paper presents a new compact analytical model of the gate leakage current in high-k based nano scale MOSFET by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semiempirical gate leakage current formulation in the BSIM 4 model. The gate tunneling currents have been calculated as a function of gate voltage for different gate dielectrics structures such as HfO2, Al2O3 and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The proposed model is compared and contrasted with santaurus simulation results to verify the accuracy of the model and excellent agreement is found between the analytical and simulated data. It is observed that proposed analytical model is suitable for different highk gate dielectrics simply by adjusting two fitting parameters. It was also shown that gate leakages reduced with the introduction of high-k gate dielectric in place of SiO2.

Keywords: Analytical model, High-k gate dielectrics, inelastic trap assisted tunneling, metal–oxide–semiconductor (MOS) devices.

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Authors: Petter Eklund, Jonathan Sjölund, Sandra Eriksson, Mats Leijon

Abstract:

The spoke type rotor can be used to obtain magnetic flux concentration in permanent magnet machines. This allows the air gap magnetic flux density to exceed the remanent flux density of the permanent magnets but gives problems with leakage fluxes in the magnetic circuit. The end leakage flux of one spoke type permanent magnet rotor design is studied through measurements and finite element simulations. The measurements are performed in the end regions of a 12 kW prototype generator for a vertical axis wind turbine. The simulations are made using three dimensional finite elements to calculate the magnetic field distribution in the end regions of the machine. Also two dimensional finite element simulations are performed and the impact of the two dimensional approximation is studied. It is found that the magnetic leakage flux in the end regions of the machine is equal to about 20% of the flux in the permanent magnets. The overestimation of the performance by the two dimensional approximation is quantified and a curve-fitted expression for its behavior is suggested.

Keywords: End effects, end leakage flux, permanent magnet machine, spoke type rotor.

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Authors: Vinod Kumar Khera, R. K. Sharma, A. K. Gupta

Abstract:

Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.

Keywords: Low power VLSI testing, independent fault, essential faults, test vector reduction.

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

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Authors: Z. Saleh, E. J. Avital, T. Korakianitis

Abstract:

The effect of the blade tip geometry of a high pressure gas turbine is studied experimentally and computationally for high speed leakage flows. For this purpose two simplified models are constructed, one models a flat tip of the blade and the second models a cavity tip of the blade. Experimental results are obtained from a transonic wind tunnel to show the static pressure distribution along the tip wall and provide flow visualization. RANS computations were carried to provide further insight into the mean flow behavior and to calculate the discharge coefficient which is a measure of the flow leaking over the tip. It is shown that in both geometries of tip the flow separates over the tip to form a separation bubble. The bubble is higher for the cavity tip while a complete shock wave system of oblique waves ending with a normal wave can be seen for the flat tip. The discharge coefficient for the flat tip shows less dependence on the pressure ratio over the blade tip than the cavity tip. However, the discharge coefficient for the cavity tip is lower than that of the flat tip, showing a better ability to reduce the leakage flow and thus increase the turbine efficiency.

Keywords: Gas turbine, blade tip leakage flow, transonic flow.

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Authors: Antonio Carlos Marques Alvim, Fernando Carvalho da Silva, Aquilino Senra Martinez

Abstract:

For a quick and accurate calculation of spatial neutron distribution in nuclear power reactors 3D nodal codes are usually used aiming at solving the neutron diffusion equation for a given reactor core geometry and material composition. These codes use a second order polynomial to represent the transverse leakage term. In this work, a nodal method based on the well known nodal expansion method (NEM), developed at COPPE, making use of this polynomial expansion was modified to treat the transverse leakage term for the external surfaces of peripheral reflector nodes. The proposed method was implemented into a computational system which, besides solving the diffusion equation, also solves the burnup equations governing the gradual changes in material compositions of the core due to fuel depletion. Results confirm the effectiveness of this modified treatment of peripheral nodes for practical purposes in PWR reactors.

Keywords: Transverse leakage, nodal expansion method, power density, PWR reactors

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Authors: L. Ashok Kumar, N. Sujith Kumar

Abstract:

Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.

Keywords: Leakage current, common mode (CM), photovoltaic (PV) systems, pulse width modulation (PWM).

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Authors: Pejman Hosseiniun, Rose Shayeghi, Iman Rahbari, Mohamad Reza Kalhor

Abstract:

CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell’s is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.

Keywords: SRAM cell, CNFET, low power, HSPICE.

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Authors: Waluyo, Ngapuli I. Sinisuka, Suwarno, Maman A. Djauhari

Abstract:

This paper presents the experimental results of discharge current phenomena on various humidity, temperature, pressure and pollutant conditions of epoxy resin specimen. The leakage distance of specimen was 3 cm, that it was supplied by high voltage. The polluted condition was given with NaCl artificial pollutant. The conducted measurements were discharge current and applied voltage. The specimen was put in a hermetically sealed chamber, and the current waveforms were analyzed with FFT. The result indicated that on discharge condition, the fifth harmonics still had dominant, rather than third one. The third harmonics tent to be appeared on low pressure heavily polluted condition, and followed by high humidity heavily polluted condition. On the heavily polluted specimen, the peaks discharge current points would be high and more frequent. Nevertheless, the specimen still had capacitive property. Besides that, usually discharge current points were more frequent. The influence of low pressure was still dominant to be easier to discharge. The non-linear property would be appear explicitly on low pressure and heavily polluted condition.

Keywords: discharge current, third harmonic, fifth harmonic, epoxy resin, non-linear.

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Authors: Mitsuhiro Taniyama, Yuu Hidaka, Masato Arai, Satoshi Kai, Hiromi Igawa, Hiroshi Yajima, Ryoichi Sasaki

Abstract:

Along with the progress of our information society, various risks are becoming increasingly common, causing multiple social problems. For this reason, risk communications for establishing consensus among stakeholders who have different priorities have become important. However, it is not always easy for the decision makers to agree on measures to reduce risks based on opposing concepts, such as security, privacy and cost. Therefore, we previously developed and proposed the “Multiple Risk Communicator" (MRC) with the following functions: (1) modeling the support role of the risk specialist, (2) an optimization engine, and (3) displaying the computed results. In this paper, MRC program version 1.0 is applied to the personal information leakage problem. The application process and validation of the results are discussed.

Keywords: Decision Making, Personal Information Leakage Problem, Risk Communication, Risk Management

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Authors: R. Bremananth

Abstract:

Acoustic Imaging based sound localization using microphone array is a challenging task in digital-signal processing. Discrete Fourier transform (DFT) based near-field acoustical holography (NAH) is an important acoustical technique for sound source localization and provide an efficient solution to the ill-posed problem. However, in practice, due to the usage of small curtailed aperture and its consequence of significant spectral leakage, the DFT could not reconstruct the active-region-of-sound (AROS) effectively, especially near the edges of aperture. In this paper, we emphasize the fundamental problems of DFT-based NAH, provide a solution to spectral leakage effect by the extrapolation based on linear predictive coding and 2D Tukey windowing. This approach has been tested to localize the single and multi-point sound sources. We observe that incorporating extrapolation technique increases the spatial resolution, localization accuracy and reduces spectral leakage when small curtail aperture with a lower number of sensors accounts.

Keywords: Acoustic Imaging, Discrete Fourier Transform (DFT), k-space wavenumber, Near-Field Acoustical Holography (NAH), Source Localization, Spectral Leakage.

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