{"title":"Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies","authors":"Zina Saheb, Ezz El-Masry","volume":104,"journal":"International Journal of Electronics and Communication Engineering","pagesStart":857,"pagesEnd":862,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/10002183","abstract":"As the Silicon oxide scaled down in MOSFET\r\ntechnology to few nanometers, gate Direct Tunneling (DT) in\r\nFloating gate (FGMOSFET) devices has become a major concern for\r\nanalog designers. FGMOSFET has been used in many low-voltage\r\nand low-power applications, however, there is no accurate model that\r\naccount for DT gate leakage in nano-scale. This paper studied and\r\nanalyzed different simulation models for FGMOSFET using TSMC\r\n90-nm technology. The simulation results for FGMOSFET cascade\r\ncurrent mirror shows the impact of DT on circuit performance in\r\nterms of current and voltage without the need for fabrication. This\r\nworks shows the significance of using an accurate model for\r\nFGMOSFET in nan-scale technologies.","references":"[1] J. Ramirez-Angulo, S. C. Choi and G. Gonzalez-Altamirano. Lowvoltage\r\ncircuits building blocks using multiple-input floating-gate\r\ntransistors. Circuits and Systems I: Fundamental Theory and\r\nApplications, IEEE Transactions on 42(11), pp. 971-974. 1995.\r\n[2] S. Sharma, S. S. Rajput, L. K. Magotra and S. S. Jamuar. FGMOS based\r\nwide range low voltage current mirror and its applications. Presented at\r\nCircuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific\r\nConference On. 2002,. DOI: 10.1109\/APCCAS.2002.1115251.\r\n[3] D. I. R. Chavez, J. de la Cruz Alejo and J. C. S. Garcia. Design of S?\r\nModulators using FGMOS transistors. Presented at Electrical\r\nEngineering Computing Science and Automatic Control (CCE), 2011\r\n8th International Conference On. 2011, DOI:\r\n10.1109\/ICEEE.2011.6106599.\r\n[4] J. Ramirez-Angulo, G. Gonzalez-Altamirano and S. C. Choi. Modeling\r\nmultiple-input floating-gate transistors for analog signal processing.\r\nPresented at Circuits and Systems, 1997. ISCAS '97. Proceedings of\r\n1997 IEEE International Symposium On. 1997.\r\n[5] Liming Yin, S. H. K. Embabi and E. Sanchez-Sinencio. A floating-gate\r\nMOSFET D\/A converter. Presented at Circuits and Systems, 1997.\r\nISCAS '97. Proceedings of 1997 IEEE International Symposium On.\r\n1997.\r\n[6] Ai Chen Low and P. Hasler. Cadence-based simulation of floating-gate\r\ncircuits using the EKV model. Presented at Circuits and Systems, 1999.\r\n42nd Midwest Symposium On. 1999, DOI:\r\n10.1109\/MWSCAS.1999.867228.\r\n[7] Dongwoo Lee, W. Kwong, D. Blaauw and D. Sylvester. Simultaneous\r\nsubthreshold and gate-oxide tunneling leakage current analysis in\r\nnanometer CMOS design. Presented at Quality Electronic Design, 2003.\r\nProceedings. Fourth International Symposium On. 2003. DOI:\r\n10.1109\/ISQED.2003.1194747.\r\n[8] C. Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu and R. W.\r\nDutton. Direct tunneling current model for circuit simulation. Presented at Electron Devices Meeting, 1999. IEDM '99. Technical Digest.\r\nInternational. 1999. DOI: 10.1109\/IEDM.1999.824256.\r\n[9] C. Choi, Ki-Young Nam, Zhiping Yu and R. W. Dutton. Impact of gate\r\ndirect tunneling current on circuit performance: A simulation study.\r\nElectron Devices, IEEE Transactions On 48(12), pp. 2823-2829. 2001. .\r\nDOI: 10.1109\/16.974710.\r\n[10] Z. Saheb and E. El-Masry, \"Modelling of direct tunneling gate leakage\r\ncurrent of floating-gate CMOS transistor in sub 100 nm technologies,\"\r\nAnalog Integrated Circuits and Signal Processing, 2015.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 104, 2015"}