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Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies
Abstract:As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1108302Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2743
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 Z. Saheb and E. El-Masry, "Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies," Analog Integrated Circuits and Signal Processing, 2015.