%0 Journal Article
	%A Ashwani K. Rana and  Narottam Chand and  Vinod Kapoor
	%D 2009
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 27, 2009
	%T Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics
	%U https://publications.waset.org/pdf/15954
	%V 27
	%X This paper presents a new compact analytical model of
the gate leakage current in high-k based nano scale MOSFET by
assuming a two-step inelastic trap-assisted tunneling (ITAT) process
as the conduction mechanism. This model is based on an inelastic
trap-assisted tunneling (ITAT) mechanism combined with a semiempirical
gate leakage current formulation in the BSIM 4 model. The
gate tunneling currents have been calculated as a function of gate
voltage for different gate dielectrics structures such as HfO2, Al2O3
and Si3N4 with EOT (equivalent oxide thickness) of 1.0 nm. The
proposed model is compared and contrasted with santaurus
simulation results to verify the accuracy of the model and excellent
agreement is found between the analytical and simulated data. It is
observed that proposed analytical model is suitable for different highk
gate dielectrics simply by adjusting two fitting parameters. It was
also shown that gate leakages reduced with the introduction of high-k
gate dielectric in place of SiO2.
	%P 546 - 553