%0 Journal Article %A Zina Saheb and Ezz El-Masry %D 2015 %J International Journal of Electronics and Communication Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 104, 2015 %T Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies %U https://publications.waset.org/pdf/10002183 %V 104 %X As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies. %P 857 - 861