Search results for: SNWT (silicon nanowire transistor)

Authors: Aritra Acharyya, Moumita Mukherjee, J. P. Banerjee

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A generalized method for small-signal simulation of avalanche noise in Mixed Tunneling Avalanche Transit Time (MITATT) device is presented in this paper where the effect of series resistance is taken into account. The method is applied to a millimeter-wave Double Drift Region (DDR) MITATT device based on Silicon to obtain noise spectral density and noise measure as a function of frequency for different values of series resistance. It is found that noise measure of the device at the operating frequency (122 GHz) with input power density of 1010 Watt/m2 is about 35 dB for hypothetical parasitic series resistance of zero ohm (estimated junction temperature = 500 K). Results show that the noise measure increases as the value of parasitic resistance increases.

Keywords: Noise Analysis, Silicon MITATT, Admittancecharacteristics, Noise spectral density.

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Authors: Abdulrahman M. Homadi

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As a great source of renewable energy, solar energy is considered to be one of the most important in the world, since it will be one of solutions cover the energy shortage in the future. Photovoltaic (PV) is the most popular and widely used among solar energy technologies. However, PV efficiency is fairly low and remains somewhat expensive. High temperature has a negative effect on PV efficiency and cooling system for these panels is vital, especially in warm weather conditions. This paper presents the results of a simulation study carried out on silicon solar cells to assess the effects of elevation on enhancing the efficiency of solar panels. The study included four different terrains. The study also took into account the direction of the wind hitting the solar panels. To ensure the simulation mimics reality, six silicon solar panels are designed in two columns and three rows, facing to the south at an angle of 30 ^o. The elevations are assumed to change from 10 meters to 200 meters. The results show that maximum increase in efficiency occurs when the wind comes from the north, hitting the back of the panels.

Keywords: Solar panels, elevation, wind direction, efficiency.

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Authors: Jia-Chuan Lin, Meng-Kai Hsu, Hsi-Ting Hou, Sin-Hong Liu

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The electrolyte stirring method of anodization etching process for manufacturing porous silicon (PS) is reported in this work. Two experimental setups of nature air stirring (PS-ASM) and electrolyte stirring (PS-ESM) are employed to clarify the influence of stirring mechanisms on electrochemical etching process. Compared to traditional fabrication without any stirring apparatus (PS-TM), a large plateau region of PS surface structure is obtained from samples with both stirring methods by the 3D-profiler measurement. Moreover, the light emission response is also improved by both proposed electrolyte stirring methods due to the cycling force in electrolyte could effectively enhance etch-carrier distribution while the electrochemical etching process is made. According to the analysis of statistical calculation of photoluminescence (PL) intensity, lower standard deviations are obtained from PS-samples with studied stirring methods, i.e. the uniformity of PL-intensity is effectively improved. The calculated deviations of PL-intensity are 93.2, 74.5 and 64, respectively, for PS-TM, PS-ASM and PS-ESM.

Keywords: Porous Silicon, Photoluminescence, Uniformity Carrier Stirring Method

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Authors: N. Asadi, M. Jackson

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Today, the central role of industrial robots in automation in general and in material handling in particular is crystal clear. Based on the current status of Photovoltaics and by focusing on lightweight material handling, PV industry has turned into a potential candidate for introducing a fresh “pick and place" robot technology. Thus, to examine the industry needs in this regard, firstly the best suited applications for such robotic automation,and then the essential prerequisites in PV industry should be identified. The objective of this paper is to present holistic views on the industry trends, general automation status and existing challenges facing lightweight robotic material handling in PV Silicon Wafer and Thin Film technologies. The results of this study show that currently no uniform pick and place solution prevails among PV Silicon Wafer manufacturers and the industry calls for a new robot solution to satisfy its needs in new directions.

Keywords: Automation, Material handling, Photovoltaic, Robot.

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Authors: A. Eštoková, M. Kovalčíková, A. Luptáková, A. Sičáková, M. Ondová

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Concrete durability as an important engineering property of concrete, determining the service life of concrete structures very significantly, can be threatened and even lost due to the interactions of concrete with external environment. Bio-corrosion process caused by presence and activities of microorganisms producing sulphuric acid is a special type of sulphate deterioration of concrete materials. The effects of sulphur-oxidizing bacteria Acidithiobacillus thiooxidans on various concrete samples, based on silica fume and zeolite, were investigated in laboratory during 180 days. A laboratory study was conducted to compare the performance of concrete samples in terms of the concrete deterioration influenced by the leaching of calcium and silicon compounds from the cement matrix. The changes in the elemental concentrations of calcium and silicon in both solid samples and liquid leachates were measured by using X – ray fluorescence method. Experimental studies confirmed the silica fume based concrete samples were found out to have the best performance in terms of both silicon and calcium ions leaching.

Keywords: Bio-corrosion, concrete, leaching, bacteria.

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Authors: Zheng-Kuohai, Yang-Shengsheng, Li-Zhonghua, Zhao-Lin

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Materials used on exterior spacecraft surfaces are subjected to many environmental threats which can cause degradation, atomic oxygen is one of the most threats. We prepared organic silicon atomic-oxygen-protection film using method of polymerization. This paper presented the effects on the film structure and its durability of the preparation processing, and analyzed the polymerization theory, the film structure and composition of the film. At last, we tested the film in our ground based atomic oxygen simulator, and indicated that the film worked well.

Keywords: Atomic oxygen, siloxane, protection, plasma, polymerization.

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Authors: Muhammad Waseem Ashraf, Shahzadi Tayyaba, Nitin Afzulpurkar, Asim Nisar, Adisorn Tuantranont, Erik L J Bohez

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In this paper, design, fabrication and coupled multifield analysis of hollow out-of-plane silicon microneedle array with piezoelectrically actuated microfluidic device for transdermal drug delivery (TDD) applications is presented. The fabrication process of silicon microneedle array is first done by series of combined isotropic and anisotropic etching processes using inductively coupled plasma (ICP) etching technology. Then coupled multifield analysis of MEMS based piezoelectrically actuated device with integrated 2×2 silicon microneedle array is presented. To predict the stress distribution and model fluid flow in coupled field analysis, finite element (FE) and computational fluid dynamic (CFD) analysis using ANSYS rather than analytical systems has been performed. Static analysis and transient CFD analysis were performed to predict the fluid flow through the microneedle array. The inlet pressure from 10 kPa to 150 kPa was considered for static CFD analysis. In the lumen region fluid flow rate 3.2946 μL/min is obtained at 150 V for 2×2 microneedle array. In the present study the authors have performed simulation of structural, piezoelectric and CFD analysis on three dimensional model of the piezoelectrically actuated mcirofluidic device integrated with 2×2 microneedle array.

Keywords: Coupled multifield, finite element analysis, hollow silicon microneedle, transdermal drug delivery.

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Authors: А. V. Panko, Е. V. Ablets, I. G. Kovzun, М. А. Ilyashov

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Based upon generalized analysis of modern know-how in the sphere of processing, concentration and purification of iron-ore raw materials (IORM), in particular, the most widespread ferrioxide-silicate materials (FOSM), containing impurities of phosphorus and other elements compounds, noted special role of nanotechnological initiatives in improvement of such processes. Considered ideas of role of nanoparticles in processes of FOSM carbonization with subsequent direct reduction of ferric oxides contained in them to metal phase, as well as in processes of alkali treatment and separation of powered iron from phosphorus compounds. Using the obtained results the wasteless method of solid-phase processing, concentration and purification of IORM and FOSM from compounds of phosphorus, silicon and other impurities was developed and it excels known methods of direct iron reduction from iron ores and metallurgical slimes.

Keywords: Iron ores, solid-phase reduction, nanoparticles in reduction and purification of iron from silicon and phosphorus, wasteless method of ores processing.

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Authors: Rizwan Asghar, Dake Liu

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A hardware efficient, multi mode, re-configurable architecture of interleaver/de-interleaver for multiple standards, like DVB, WiMAX and WLAN is presented. The interleavers consume a large part of silicon area when implemented by using conventional methods as they use memories to store permutation patterns. In addition, different types of interleavers in different standards cannot share the hardware due to different construction methodologies. The novelty of the work presented in this paper is threefold: 1) Mapping of vital types of interleavers including convolutional interleaver onto a single architecture with flexibility to change interleaver size; 2) Hardware complexity for channel interleaving in WiMAX is reduced by using 2-D realization of the interleaver functions; and 3) Silicon cost overheads reduced by avoiding the use of small memories. The proposed architecture consumes 0.18mm2 silicon area for 0.12μm process and can operate at a frequency of 140 MHz. The reduced complexity helps in minimizing the memory utilization, and at the same time provides strong support to on-the-fly computation of permutation patterns.

Keywords: Hardware interleaver implementation, WiMAX, DVB, block interleaver, convolutional interleaver, hardwaremultiplexing.

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Authors: Ahmed Shariful Alam, Abu Hena M. Mustafa Kamal, M. Abdul Rahman, M. Nasmus Sakib Khan Shabbir, Atiqul Islam

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According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.

Keywords: ITRS, enhancement type MOSFET, island, DC analysis, transient analysis, power consumption, background charge co-tunneling.

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Authors: Paniz Tafakori, Ali A. Orouji

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In this paper the features of multiple material gate silicon-on-insulator MOSFETs are presented and compared with single material gate silicon-on-insulator MOSFET structures. The results indicate that the multiple material gate structures reduce short channel effects such as drain induce barrier lowering, hot electron effect and better current characteristics in comparison with single material structures

Keywords: Short-channel effects (SCEs), Dual material gate (DMG), Triple material gate (TMG), Pentamerous material gate (PMG).

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Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

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This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: ESD (Electro-Static Discharge), SCR (Silicon Controlled Rectifier), holding Voltage.

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Authors: N. Sumathi, R. Srinivasa Rao

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This paper presents the experimental results of 11 kV and 33 kV silicon composite insulators under artificial salt and urea polluted conditions. The tests were carried out under different seasons like summer, winter, and monsoon. The artificial pollution is prepared by properly dissolving the salt and urea in the water. The prepared salt and urea pollutions are sprayed on the insulators and dried up for sufficiently large time. The process is continued until a uniform layer is formed on the surface of insulator. For each insulator rating, four samples were tested. The maximum leakage current and breakdown voltage were measured. From experimental data, performance of test specimen is evaluated by comparing breakdown voltage and leakage current during different seasons when exposed to salt and urea polluted conditions. From these results the performance of the insulators can be predicted when they are installed in industrial, agricultural, and coastal areas. The experimental tests were carried out in the High Voltage laboratory using two stage cascade transformer having the rating of 1000 kVA, 500 kV.

Keywords: Silicon composite insulators, Urea pollution, Leakage current, Breakdown voltage, salt pollution, artificial pollution.

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Authors: Bang-Shiuh Chen, Lien-Wen Chen

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We have devised a thermal carpet cloak theoretically and implemented in silicon using layered metamaterial. The layered metamaterial is composed of single crystalline silicon and its phononic crystal. The design is based on a coordinate transformation. We demonstrate the result with numerical simulation. Great cloaking performance is achieved as a thermal insulator is well hidden under the thermal carpet cloak. We also show that the thermal carpet cloak can even the temperature on irregular surface. Using thermal carpet cloak to manipulate the heat conduction is effective because of its low complexity.

Keywords: Metamaterial, heat conduction, cloaking, phononic crystal.

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

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Silicon photonics is merging as a unified platform for driving photonic based telecommunications and for local photonic based interconnect but it suffers from large footprint as compared with the nanoelectronics. Plasmonics is an attractive alternative for nanophotonics. In this work, two CMOS compatible plasmonic waveguide platforms are compared. One is the horizontal metal-insulator-Si-insulator-metal nanoplasmonic waveguide and the other is metal-insulator-Si hybrid plasmonic waveguide. Various passive and active photonic devices have been experimentally demonstrated based on these two plasmonic waveguide platforms.

Keywords: Plasmonics, on-chip integration, Silicon photonics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

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Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

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The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: Threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation.

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Authors: Zone-Ching Lin, Meng-Hua Lin, Ying-Chih Hsu

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This paper uses quasi-steady molecular statics model and diamond tool to carry out simulation temperature rise of nanoscale orthogonal cutting single-crystal silicon. It further qualitatively analyzes temperature field of silicon workpiece without considering heat transfer and considering heat transfer. This paper supposes that the temperature rise of workpiece is mainly caused by two heat sources: plastic deformation heat and friction heat. Then, this paper develops a theoretical model about production of the plastic deformation heat and friction heat during nanoscale orthogonal cutting. After the increased temperature produced by these two heat sources are added up, the acquired total temperature rise at each atom of the workpiece is substituted in heat transfer finite difference equation to carry out heat transfer and calculates the temperature field in each step and makes related analysis.

Keywords: Quasi-steady molecular statics, Nanoscale orthogonal cutting, Finite difference, Temperature.

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Authors: D.N Awang Sh'ri, E. Hamzah

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The deposition of diamond films on a Si3N4 substrate is an attractive technique for industrial applications because of the excellent properties of diamond. Pretreatment of substrate is very important prior to diamond deposition to promote nucleation and adhesion between coating and substrate. Deposition of nanocrystalline diamonds films on silicon nitride substrate have been carried out by HF-CVD technique using mixture of methane and hydrogen gases. Different pretreatment of substrate including chemical etching consists of hot acid etching and basic etching and mechanical etching were used to study the quality of diamond formed on the substrate. The structure and morphology of diamond coating have been studied using X-ray Diffraction (XRD) and Scanning Electron Microscope (SEM) while diamond film quality has been characterized using Raman spectroscopy. AFM was used to investigate the effect of chemical etching and mechanical pretreatment on the surface roughness of the substrates and the resultant morphology of nanocrystalline diamond. It was found that diamond film deposited on as-received, basic etched and grinded substrate shows the morphology of cauliflower while blasted and acidic etched substrates produce smooth, continuous diamond film. However, the Raman investigation did not show any deviation in quality of diamond film for any pretreatment.

Keywords: Nanocrystalline diamond, Chemical VaporDeposition, Pretreatment, Silicon Nitride

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

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In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: Jianwen Li, Hongfang Ma, Weixin Qian, Haitao Zhang, Weiyong Ying

Abstract:

Methanol-to-propylene conversion was carried out in a continuous-flow fixed-bed reactor over nano-sized HZSM-5 zeolites. The HZSM-5 catalysts were synthesized with different Si/Al ratio and silicon sources, and treated with NaOH. The structural property, morphology, and acidity of catalysts were measured by XRD, N₂ adsorption, FE-SEM, TEM, and NH₃-TPD. The results indicate that the increment of Si/Al ratio decreased the acidity of catalysts and then improved propylene selectivity, while silicon sources had slight impact on the acidity but affected the product distribution. The desilication after alkali treatment could increase intracrystalline mesopores and enhance propylene selectivity.

Keywords: Alkali treatment, HZSM-5, methanol-to-propylene, synthesis condition.

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

Abstract:

Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Smaali Assia, Outemzabet Ratiba, Media El Mahdi, Kadi Mohamed

Abstract:

Films of pure tin oxide SnO2 and in presence of antimony atoms (SnO2-Sb) deposited onto glass substrates have shown a sufficiently high energy gap to be transparent in the visible region, a high electrical mobility and a carrier concentration which displays a good electrical conductivity [1]. In this work, the effects of polycrystalline silicon substrate on the optical properties of pure and Sb doped tin oxide is investigated. We used the APCVD (atmospheric pressure chemical vapour deposition) technique, which is a low-cost and simple technique, under nitrogen ambient, for growing this material. A series of SnO2 and SnO2-Sb have been deposited onto polycrystalline silicon substrates with different contents of antimony atoms at the same conditions of deposition (substrate temperature, flow oxygen, duration and nitrogen atmosphere of the reactor). The effect of the substrate in terms of morphology and nonlinear optical properties, mainly the reflectance, was studied. The reflectance intensity of the device, compared to the reflectance of tin oxide films deposited directly on glass substrate, is clearly reduced on the overall wavelength range. It is obvious that the roughness of the poly-c silicon plays an important role by improving the reflectance and hence the optical parameters. A clear shift in the minimum of the reflectance upon doping level is observed. This minimum corresponds to strong free carrier absorption, resulting in different plasma frequency. This effect is followed by an increase in the reflectance depending of the antimony doping. Applying the extended Drude theory to the combining optical and electrical obtained results these effects are discussed.

Keywords: Doping, oxide, reflectance.

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Authors: T. Brettschneider, C. Dorrer, H. Suy, T. Braun, E. Jung, R. Hoofman, M. Bründel, R. Zengerle, F. Lärmer

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We present an integration approach of a CMOS biosensor into a polymer based microfluidic environment suitable for mass production. It consists of a wafer-level-package for the silicon die and laser bonding process promoted by an intermediate hot melt foil to attach the sensor package to the microfluidic chip, without the need for dispensing of glues or underfiller. A very good condition of the sensing area was obtained after introducing a protection layer during packaging. A microfluidic flow cell was fabricated and shown to withstand pressures up to Δp = 780 kPa without leakage. The employed biosensors were electrically characterized in a dry environment.

Keywords: CMOS biosensor, laser bonding, silicon polymer integration, wafer level packaging.

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Authors: Muhibul Haque Bhuyan

Abstract:

This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO₂), aluminum silicate (Al₂SiO₅), silicon nitride (Si₃N₄), alumina (Al₂O₃), hafnium silicate (HfSiO₄), tantalum pentoxide (Ta₂O₅), hafnium dioxide (HfO₂), zirconium dioxide (ZrO₂), and lanthanum oxide (La₂O₃) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.

Keywords: Linear symmetric pocket profile, pocket implanted n-MOS Device, model, impact of gate material, insulator thickness.

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Authors: V. E. Messerle, O. A. Lavrichshev, A. B. Ustimenko

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The article presents a plasma chemical technology for processing solid fuels, using examples of bituminous and brown coals. Thermodynamic and experimental investigation of the technology was made. The technology allows producing synthesis gas from the coal organic mass and valuable components (technical silicon, ferrosilicon, aluminum, and carbon silicon, as well as microelements of rare metals, such as uranium, molybdenum, vanadium, etc.) from the mineral mass. The thusly produced highcalorific synthesis gas can be used for synthesis of methanol, as a high-calorific reducing gas instead of blast-furnace coke as well as power gas for thermal power plants.

Keywords: Gasification, mineral mass, organic mass, plasma, processing, solid fuel, synthesis gas, valuable components.

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Authors: P. Asadee

Abstract:

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

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In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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