Robust & Energy Efficient Universal Gates for High Performance Computer Networks at 22nm Process Technology
Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1336502Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2146
 Tiwari, V et al., "Reducing power in high-performance microprocessors”, Proceedings of Design Automation Conference, 1998, pp.732–737.
 Sumeer Goel, Ashok Kumar and Magdy A. Bayoumi, "Design of Robust Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style”, IEEE Transactions on VLSI Systems, Vol. 14, pp. 1309–1321, 2006.
 Radhakrishnan D, Whitaker S.R., and Maki G.K., "Formal design procedures for pass transistor switching circuits”, IEEE J. Solid State Circuits, Vol. 20, pp. 531–535, 1985.
 M. Geetha Priya, K. Baskaran, D. Krishnaveni and S. Srinivasan, "A New Leakage Power Reduction Technique for CMOS VLSI Circuits”, Journal of Artificial Intelligence, Vol. 5, pp. 227-232, 2012.
 K. Baskaran et al., "Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications”, The International Conference on Communication Technology and System Design, pp. 1163 – 1170, 2011.
 Geetha Priya M. and Baskaran K., "A Novel Low Power 3 Transistor based Universal Gate for VLSI Applications”, Journal of Scientific & Industrial Research, Vol. 72, pp.217-221, 2013.
 D.Krishnaveni et al., "A Novel Leakage Power Reduction Technique for CMOS VLSI Circuits”, European Journal of Scientific Research, Vol.74, pp. 96-105, 2012.
 Geetha Priya, M and Baskaran, K , "A New Universal Gate for Low Power SoC Applications”, Sadhana - Academy Proceedings in Engineering Sciences, Vol. 38, pp. 645–65, 2013.
 Chiraz Khedhiri, Mouna Karmani and Belgacem Hamdi, "A Differential Double Pass Transistor Logic Unit”, The International Journal of Computer Science Issues, Vol. 9, pp. 351–354, 2012.
 Makoto Suzuki et al., "A 1.5 ns 32 b CMOS ALU in Double Pass – Transistor Logic”, ISSCC Dig Tech Papers, pp. 90-91, 1993.
 Yano K et al., "A 3.8 ns CMOS 16x16-b Multiplier Using Complementary Pass – Transistor Logic”, IEEE J. Solid State Circuits, Vol. 25, pp. 388–395, 1990.
 Lixin Gao, "High Performance Complementary Pass Transistor Logic Full Adder”, Proc. International Conference on Electronic and Mechanical Engineering and Information Technology, pp. 4306–4309, 2011.
 Akilesh Parameswar, et al., "A Swing Restored Pass – Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proc. IEEE Custom Integrated Circuit Conference, Vol.31, pp. 804-809, 1996.
 K. Yip and D. Al-Khalili, "Multilevel logic synthesis using hybrid pass logic and CMOS topologies”, IEE Proceedings, Circuits, Devices and Systems, Vol.150, pp. 445–452, 2003.
 V.G. Oklobdzija and B. Duchene, "Pass-Transistor Dual Value Logic for Low-Power CMOS,” of Proc International Symposium on VLSI Technology, Systems, and Applications, pp. 341–344, 1995.