Commenced in January 2007
Paper Count: 31430
A Silicon Controlled Rectifier-Based ESD Protection Circuit with High Holding Voltage and High Robustness Characteristics
Abstract:In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1316678Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 528
 R.G Wagner, J. Soden and C.F. Hawkins “Extend and Cost of EOS/ESD Damage in an IC Manufacturing Process”, in Porc. of the 15th EOS/ESD Symp., pp.49-55, 1993.
 Yong Seo Koo, et. al., “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.
 Sheng-Lyang Jang, et. al., “Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,” Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.
 P.-Y Ran, M. Indrajjit, P.-H. Li and S. H. Voldman. “RC-triggered PNP and NPN Simultaneously Switched Silicon Controlled Rectrifier ESD Networks for Sub-0.18um Technology” in proc. Of IEEE int. symp. On physical and failure Analysis of Intergrated Circuits, pp. 71-75, 2005.
 W.Y Chen, et. al., “Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,” device and system, APCCAS 2008, pp. 61-64, 2008.
 Amerasekera A., Duvvury Charvaka “ESD in Silicon Integrated Circuits”, New York:John Wiley and Sons, 2002.
 Albert Z. H. Wang, “On-chip ESD Protection for Integrated Circuits”, Kluwer Academic Publisher Group, 2002.
 O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," EOS/ESD Symp, pp. 77-86, 2006.
 K. D Kim "A Study on the Novel SCR Nano ESD Protection Device Design and Fabrication," j.inst. Korean. electr. electron. eng, vol. 9, no. 2, pp. 83-91, 2005.
 M. D. Ker and H. H. Chang, “How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,” J. Electro- statics, vol. 47, pp.215-248, 1999.
 Y. Koo, K. Lee, K. Kim, and J. Kwon, “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, vol. 40, pp. 1007-1012, 2009.
 S.-L. Jang, L.-S. Lin, and S.-H. Li, “Temperature-dependent dynamic trig-gering characteristics of SCR-type ESD protection circuits,” Solid-State Electronics, vol. 45, pp. 2005-2009, 2001.