Analysis of SCR-Based ESD Protection Circuit on Holding Voltage Characteristics
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Analysis of SCR-Based ESD Protection Circuit on Holding Voltage Characteristics

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: ESD (Electro-Static Discharge), SCR (Silicon Controlled Rectifier), holding Voltage.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1093498

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References:


[1] Huang, et al.., "ESD protection design for advanced CMOS,” in Proc. SPIE, 2001, pp. 123-131.
[2] S. P. Bingulac, "On the compatibility of adaptive controllers (Published Conference Proceedings style),” in Proc. 4th Annu. Allerton Conf. Circuits and Systems Theory, New York, 1994, pp. 8–16.
[3] M. -D. Ker; C. -Y. Wu, T. Cheng, M. J. -N. Wu, T. -L. Yu, and A.C. Wang, "WholechipESD protection for CMOS VLSI/ULSI with multiple power pins,” Proc. of theInt.Integrated Reliability Workshop, pp. 124–128, 1994..
[4] C. Russ, M. Mergens, J. Armer, p. jozwiak, G. Kolluri, L. Avery, and K. Verhaege, "GGSCRs: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes,” in Proc. EOS/ESD Symp., 2001, pp.22-31.
[5] M.-D. Ker and K.-C. Hsu, "overview of on-chip electrostatic discharge protection design with SCR-vased devices in CMOS intergrated circuits,” IEEE Tran. Device Mater. Reliab. Vol. 5, no. 2, Jun 2005, pp.235-249.
[6] P.-Y.Tan, M. Indrajit, p.-H. Li, and S.H.Voldman, "Rc-triggered PNP and NPN simultaneously switched silicon controlled rectifier ESD networks for sub-0.18um technology,” in Proc. Of IEEE Int. Symp. On Physical and Failure Analysis of Integrated Circuits, 2005, pp. 71-75.
[7] M. D. Ker and K. C. Hsu, "Latchup-free ESD protection design with complementary substrate-triggered SCR devices,” IEEE J. Solid State Cir., vol. 38, No. 8, pp. 1380-1392,2003
[8] M. –D. Ker and W. –Y. Lo, "Design on the low-leakage diode string for using in the power-rail ESD clmp circuits in a 0.35-μm silicide CMOS process,” IEEE J. of Solid-State Cir., vol. 35, No. 4, pp. 601-11,2000