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3.5-bit Stage of the CMOS Pipeline ADC

Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua


A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.

Keywords: pipelined ADC, MDAC, operational amplifier.

Digital Object Identifier (DOI):

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[1] P. R.Gray, R.G Meyer. Analysis and Design of Analog Integrated Circuits,2nd Edition New York: Wiley,1982
[2] Waltari M E, Halonen K A I. Circuit techniques for low-voltage and high speed A/D converters (M). Dordrecht, Netherlands, Kluwer Academic Publisher, 2002
[3] Y. Yoshii, K. Asano, M. Nakamura, et al. An 8b 100MSPS Flash ADC. ISSCC Dig. Tech. Papers, San Francisco, CA: IEEE Solid-State Circuits Society, 1984, 58-59
[4] Liu Chang-Wei. A loop charge method for the Z-domain analysis of switched-capacitor networks. Journal of electronics & information technology, 1994, 16(1) : 96-101
[5] Byung-Moo Min, Peter Kim, Frederick W. Bowman, David M. Boisvert and Aelo J.Aude. A 69mW 10bit 80MSPS Pipelined CMOS ADC(J). IEEE J. Solide-State Circuits, 2003,38(12):2031-2039.
[6] Hernes B, Briskemyr A., et al. A 1.2V 220MSPS 10bit pipeline ADC implemented in 0.13um digital CMOS(C). IEEE International on Solid-State Circuits Conference, 2004, vol.1, PP:256-262.