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A Low Power High Frequency CMOS RF Four Quadrant Analog Mixer

Authors: M. Aleshams, A. Shahsavandi


This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: multiplier, RF-Mixer, cut-off frequency, power consumption

Digital Object Identifier (DOI):

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