Design and Analysis of Low-Power, High Speed and Area Efficient 2-Bit Digital Magnitude Comparator in 90nm CMOS Technology Using Gate Diffusion Input
Authors: Fasil Endalamaw
Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 305
 M. W. Allam, New methodologies for low-power high-performance digital VLSI design, 2000.
 N. S. Kim et al., "Leakage current: Moore's law meets static power," in Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
 J. Rabaey and A. Chandrakasan, Digital Integrated Circuits: A Design Perspective. Pearson Education, 2003.
 L. Xiu, VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy. Piscataway, NJ: IEEE Press, 2007.
 A. K. Maini, Digital electronics: principles, devices, and applications. Chichester, England: John Wiley & Sons, 2007.
 N. H. E. Weste and D. M. Harris, CMOS VLSI design: A circuits and systems perspective. Boston, MA: Addison-Wesley, 2011.
 D. Radhakrishnan, S. R. Whitaker and G. K. Maki, "Formal design procedures for pass transistor switching circuits," in IEEE Journal of Solid-State Circuits, vol. 20, no. 2, pp. 531-536, April 1985.
 S.-M. Kang and Y. Leblebici, CMOS digital integrated circuits: analysis and design, 3rd ed. New York: McGraw-Hill, 2002.
 J. P. Uyemura, Circuit design for CMOS VLSI. New York: Springer Science Business Media, LLC, 1992.
 A. Morgenshtein, A. Fish, and I. A. Wagner, "Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization," 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), Phoenix-Scottsdale, AZ, USA, 2002, pp. I-I.
 P. Balasubramanian and J. Joh, "Low power digital design using modified GDI method," International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., Tunis, 2006, pp. 190-193.
 A. Morgenshtein, A. Fish and I. A. Wagner, "Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566-581, Oct. 2002.
 R. Uma and P. Dhavachelvan, "Modified gate diffusion input technique: a new technique for enhancing performance in full adder circuits." Procedia Technology, vol. 6, no. 2, pp. 74-81, 2012.