Search results for: floating gate MOSFETs

Authors: Buket Turan Azizoğlu

Abstract:

In switch mode power inverters, small sized inverters can be obtained by increasing the switching frequency. Switching frequency increment causes high driver losses. Also, high dt di and dt dv produced by the switching action creates high Electromagnetic Interference (EMI) and Radio Frequency Interference (RFI). In this paper, a series half bridge series resonant inverter circuit is simulated and evaluated practically to demonstrate the turn-on and turn-off conditions during zero or close to zero voltage switching. Also, the reverse recovery current effects of the body diode of the MOSFETs were investigated by operating above and below resonant frequency.

Keywords: Driver losses, Half Bridge series resonant inverter, Zero Voltage Switching

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

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In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: Jun Wang, Tingcun Wei

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The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, PLL megafunction, FPGA, time resolution, digitally-controlled DC-DC switching converter.

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

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Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: Padmanabhan Balasubramanian, C. Ardil

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In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: H. Bentarzi, A. Zitouni

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The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: Amplifier class D, FPGA, protective relay, tester.

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Authors: A. Hamdoune, M. Abdelmoumene, A. Hamroun

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The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures.

We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (f_T) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Keywords: n-GaN/AlGaN/GaN HEMT, drain-source current (IDS), transconductance (gm), cut-off frequency (fT), maximum oscillation frequency (fmax).

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Authors: Ali Heidari

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This paper presents the principles for improving flood mitigation operation in multipurpose dams and maximizing reservoir performance during flood occurrence with a focus on the real-time operation of gated spillways. The criteria of operation include the safety of dams during flood management, minimizing the downstream flood risk by decreasing the flood hazard and fulfilling water supply and other purposes of the dam operation in mid and long terms horizons. The parameters deemed to be important include flood inflow, outlet capacity restrictions, downstream flood inundation damages, economic revenue of dam operation, and environmental and sedimentation restrictions. A simulation model was used to determine the real-time release of the Dez Dam located in the Dez Rivers in southwest Iran, considering the gate regulation curves for the gated spillway. The results of the simulation model show that there is a possibility to improve the current procedures used in the real-time operation of the dams, particularly using gate regulation curves and early flood forecasting system results. The Dez Dam operation data show that in one of the best flood control records, 17% of the total active volume and flood control pool of the reservoir have not been used in decreasing the downstream flood hazard despite the availability of a flood forecasting system.

Keywords: Dam operation, flood control criteria, Dez Dam, Iran.

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Authors: Khaled A. Madi

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Induction motors are being used in greater numbers throughout a wide variety of industrial and commercial applications because it provides many benefits and reliable device to convert the electrical energy into mechanical motion. In some application it-s desired to control the speed of the induction motor. Because of the physics of the induction motor the preferred method of controlling its speed is to vary the frequency of the AC voltage driving the motor. In recent years, with the microcontroller incorporated into an appliance it becomes possible to use it to generate the variable frequency AC voltage to control the speed of the induction motor. This study investigates the microcontroller based variable frequency power inverter. the microcontroller is provide the variable frequency pulse width modulation (PWM) signal that control the applied voltage on the gate drive, which is provides the required PWM frequency with less harmonics at the output of the power inverter. The fully controlled bridge voltage source inverter has been implemented with semiconductors power devices isolated gate bipolar transistor (IGBT), and the PWM technique has been employed in this inverter to supply the motor with AC voltage. The proposed drive system for three & single phase power inverter is simulated using Matlab/Simulink. The Matlab Simulation Results for the proposed system were achieved with different SPWM. From the result a stable variable frequency inverter over wide range has been obtained and a good agreement has been found between the simulation and hardware of a microcontroller based single phase inverter.

Keywords: Power, inverter, PWM, microcontroller.

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Authors: Ming-Hsiang Shih, Wen-Pei Sung, Shih-Heng Tung

Abstract:

The purposes of hydraulic gate are to maintain the functions of storing and draining water. It bears long-term hydraulic pressure and earthquake force and is very important for reservoir and waterpower plant. The high tensile strength of steel plate is used as constructional material of hydraulic gate. The cracks and rusts, induced by the defects of material, bad construction and seismic excitation and under water respectively, thus, the mechanics phenomena of gate with crack are probing into the cause of stress concentration, induced high crack increase rate, affect the safety and usage of hydroelectric power plant. Stress distribution analysis is a very important and essential surveying technique to analyze bi-material and singular point problems. The finite difference infinitely small element method has been demonstrated, suitable for analyzing the buckling phenomena of welding seam and steel plate with crack. Especially, this method can easily analyze the singularity of kink crack. Nevertheless, the construction form and deformation shape of some gates are three-dimensional system. Therefore, the three-dimensional Digital Image Correlation (DIC) has been developed and applied to analyze the strain variation of steel plate with crack at weld joint. The proposed Digital image correlation (DIC) technique is an only non-contact method for measuring the variation of test object. According to rapid development of digital camera, the cost of this digital image correlation technique has been reduced. Otherwise, this DIC method provides with the advantages of widely practical application of indoor test and field test without the restriction on the size of test object. Thus, the research purpose of this research is to develop and apply this technique to monitor mechanics crack variations of weld steel hydraulic gate and its conformation under action of loading. The imagines can be picked from real time monitoring process to analyze the strain change of each loading stage. The proposed 3-Dimensional digital image correlation method, developed in the study, is applied to analyze the post-buckling phenomenon and buckling tendency of welded steel plate with crack. Then, the stress intensity of 3-dimensional analysis of different materials and enhanced materials in steel plate has been analyzed in this paper. The test results show that this proposed three-dimensional DIC method can precisely detect the crack variation of welded steel plate under different loading stages. Especially, this proposed DIC method can detect and identify the crack position and the other flaws of the welded steel plate that the traditional test methods hardly detect these kind phenomena. Therefore, this proposed three-dimensional DIC method can apply to observe the mechanics phenomena of composite materials subjected to loading and operating.

Keywords: Welded steel plate, crack variation, three-dimensional Digital Image Correlation (DIC).

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Authors: B. Mahmoud, M.H. Bedoui, R. Raychev, H. Essabbah

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We present in this paper an acquisition and treatment system designed for semi-analog Gamma-camera. It consists of a nuclear medical Image Acquisition, Treatment and Display chain(IATD) ensuring the acquisition, the treatment of the signals(resulting from the Gamma-camera detection head) and the scintigraphic image construction in real time. This chain is composed by an analog treatment board and a digital treatment board. We describe the designed systems and the digital treatment algorithms in which we have improved the performance and the flexibility. The digital treatment algorithms are implemented in a specific reprogrammable circuit FPGA (Field Programmable Gate Array).interface for semi-analog cameras of Sopha Medical Vision(SMVi) by taking as example SOPHY DS7. The developed system consists of an Image Acquisition, Treatment and Display (IATD) ensuring the acquisition and the treatment of the signals resulting from the DH. The developed chain is formed by a treatment analog board and a digital treatment board designed around a DSP [2]. In this paper we have presented the architecture of a new version of our chain IATD in which the integration of the treatment algorithms is executed on an FPGA (Field Programmable Gate Array)

Keywords: Nuclear medical image, scintigraphic image, digitaltreatment, linearity, spectrometry, FPGA.

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Authors: Rehab Abdullah Shendi

Abstract:

The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: Customisation, FPGA, MIPS, partial reconfiguration.

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Authors: S. Chuenchooklin, T. Ichikawa, P. Mekpruksawong

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This research was conducted in the Lower Namkam Irrigation Project situated in the Namkam River Basin in Thailand. Degradation of groundwater quality in some areas is caused by saline soil spots beneath ground surface. However, the tail regulated gate structure on the Namkam River, a lateral stream of the Mekong River. It is aimed for maintaining water level in the river at +137.5 to +138.5 m (MSL) and flow to the irrigation canals based on a gravity system since July 2009. It might leach some saline soil spots from underground to soil surface if lack of understanding of the conjunctive surface water and groundwater behaviors. This research has been conducted by continuously the observing of both shallow and deep groundwater level and quality from existing observation wells. The simulation of surface water was carried out using a hydrologic modeling system (HEC-HMS) to compute the ungauged side flow catchments as the lateral flows for the river system model (HEC-RAS). The constant water levels in the upstream of the operated gate caused a slight rising up of shallow groundwater level when compared to the water table. However, the groundwater levels in the confined aquifers remained less impacted than in the shallow aquifers but groundwater levels in late of wet season in some wells were higher than the phreatic surface. This causes salinization of the groundwater at the soil surface and might affect some crops. This research aims for the balance of water stage in the river and efficient groundwater utilization in this area.

Keywords: Surface water, groundwater observation, irrigation, water balance.

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Authors: Mohamed Fathy Heweage, Xiao Wen, Ayman Mokhtar, Ahmed Eldamarawy

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In this paper, we are interested in modeling, simulation, and measurement of the laser spot position with a quadrant detector. We enhance detection and tracking of semi-laser weapon decoding system based on microcontroller. The system receives the reflected pulse through quadrant detector and processes the laser pulses through a processing circuit, a microcontroller decoding laser pulse reflected by the target. The seeker accuracy will be enhanced by the decoding system, the laser detection time based on the receiving pulses number is reduced, a gate is used to limit the laser pulse width. The model is implemented based on Pulse Repetition Frequency (PRF) technique with two microcontroller units (MCU). MCU1 generates laser pulses with different codes. MCU2 decodes the laser code and locks the system at the specific code. The codes EW selected based on the two selector switches. The system is implemented and tested in Proteus ISIS software. The implementation of the full position determination circuit with the detector is produced. General system for the spot position determination was performed with the laser PRF for incident radiation and the mechanical system for adjusting system at different angles. The system test results show that the system can detect the laser code with only three received pulses based on the narrow gate signal, and good agreement between simulation and measured system performance is obtained.

Keywords: 4-quadrant detector, pulse code detection, laser guided weapons, pulse repetition frequency, ATmega 32 microcontrollers.

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Authors: V.K.Ananthashayana, Geetha.K.S

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In this paper, a recursive algorithm for the computation of 2-D DCT using Ramanujan Numbers is proposed. With this algorithm, the floating-point multiplication is completely eliminated and hence the multiplierless algorithm can be implemented using shifts and additions only. The orthogonality of the recursive kernel is well maintained through matrix factorization to reduce the computational complexity. The inherent parallel structure yields simpler programming and hardware implementation and provides log 1 2 3 2 N N-N+ additions and N N 2 log 2 shifts which is very much less complex when compared to other recent multiplierless algorithms.

Keywords: DCT, Multilplerless, Ramanujan Number, Recursive.

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Authors: C. L. Toh, N. R. N. Idris, A. H. M. Yatim

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This paper introduces a new digital logic design, which combines the DSP and FPGA to implement the conventional DTC of induction machine. The DSP will be used for floating point calculation whereas the FPGA main task is to implement the hysteresis-based controller. The emphasis is on FPGA digital logic design. The simulation and experimental results are presented and summarized.

Keywords: DTC, DSP, FPGA, induction machine

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Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

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In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: Z. Harouni, L. Osman, M. Yeddes, A. Gharsallah, H. Baudrand

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In this paper, an efficient wave concept iterative process (WCIP) with auxiliary Sources is presented for full wave investigation of an active microwave structure on micro strip technology. Good agreement between the experimental and simulation results is observed.

Keywords: WCIP, Dual-Gate Transistor, Auxiliary source.

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Authors: Shibesh Dutta, Sivaramakrishnan R., Sundar Gopalan, Balakrishnan Shankar

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MOSCAPs of various combinations of Hafnium oxide and Titanium oxide of varying thickness with Aluminum as gate electrode have been fabricated and electrically characterized. The effects of voltage stress on the I-V characteristics for prolonged time durations have been studied and compared. Results showed hard breakdown and negligible degradation of reliability under stress.

Keywords: breakdown, MOSCAP, voltage stress.

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Authors: Alloysius C. Ogodo, Ositadinma C. Ugbogu, Uzochukwu G. Ekeleme

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Food poisoning and infection by bacteria are of public health significance to both developing and developed countries. Samples of ogi (akamu) prepared from white and yellow variety of maize sold in Uturu and Okigwe were analyzed together with the laboratory prepared ogi for bacterial quality using the standard microbiological methods. The analyses showed that both white and yellow variety had total bacterial counts (cfu/g) of 4.0 ×107 and 3.9 x 107 for the laboratory prepared ogi while the commercial ogi had 5.2 x 107 and 4.9 x107, 4.9 x107 and 4.5 x107, 5.4 x107 and 5.0 x107 for Eke-Okigwe, Up-gate and Nkwo-Achara market respectively. The Staphylococcal counts ranged from 2.0 x 102 to 5.0 x102 and 1.0 x 102 to 4.0 x102 for the white and yellow variety from the different markets while Staphylococcal growth was not recorded on the laboratory prepared ogi. The laboratory prepared ogi had no Coliform growth while the commercially prepared ogi had counts of 0.5 x103 to 1.6 x 103 for white variety and 0.3 x 103 to 1.1 x103 for yellow variety respectively. The Lactic acid bacterial count of 3.5x106 and 3.0x106 was recorded for the laboratory ogi while the commercially prepared ogi ranged from 3.2x106 to 4.2x106 (white variety) and 3.0 x106 to 3.9 x106 (yellow). The presence of bacteria isolates from the commercial and laboratory fermented ogi showed that Lactobacillus sp, Leuconostoc sp and Citrobacter sp were present in all the samples, Micrococcus sp and Klebsiella sp were isolated from Eke- Okigwe and ABSU-up-gate markets varieties respectively, E. coli and Staphylococcus sp were present in Eke-Okigwe and Nkwo- Achara markets while Salmonella sp were isolated from the three markets. Hence, there are chances of contracting food borne diseases from commercially prepared ogi. Therefore, there is the need for sanitary measures in the production of fermented cereals so as to minimize the rate of food borne pathogens during processing and storage.

Keywords: Bacterial quality, fermentation, maize, Ogi.

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Authors: Niveditha Domse, Kris Kumar, K. N. Balasubramanya Murthy

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The more recent satellite projects/programs makes extensive usage of real – time embedded systems. 16 bit processors which meet the Mil-Std-1750 standard architecture have been used in on-board systems. Most of the Space Applications have been written in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are needed in the area of spacecraft computing and therefore an effort is desirable in the study and survey of 64 bit architectures for space applications. This will also result in significant technology development in terms of VLSI and software tools for ADA (as the legacy code is in ADA). There are several basic requirements for a special processor for this purpose. They include Radiation Hardened (RadHard) devices, very low power dissipation, compatibility with existing operational systems, scalable architectures for higher computational needs, reliability, higher memory and I/O bandwidth, predictability, realtime operating system and manufacturability of such processors. Further on, these may include selection of FPGA devices, selection of EDA tool chains, design flow, partitioning of the design, pin count, performance evaluation, timing analysis etc. This project deals with a brief study of 32 and 64 bit processors readily available in the market and designing/ fabricating a 64 bit RISC processor named RISC MicroProcessor with added functionalities of an extended double precision floating point unit and a 32 bit signal processing unit acting as co-processors. In this paper, we emphasize the ease and importance of using Open Core (OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as Icarus to develop FPGA based prototypes quickly. Commercial tools such as Xilinx ISE for Synthesis are also used when appropriate.

Keywords: RISC MicroProcessor, RPC – RISC Processor Core, PBX – Processor to Block Interface part of the Interconnection Network, BPX – Block to Processor Interface part of the Interconnection Network, FPU – Floating Point Unit, SPU – Signal Processing Unit, WB – Wishbone Interface, CTU – Clock and Test Unit

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Authors: Alessandro A. Zizzari, Francesca Calabrese, Giovanni Indiveri, Andrea Coraddu, Diego Villa

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The aim of this paper is to present a comparative study on two different methods for the evaluation of the equilibrium point of a ship, core issue for designing an On Board Stability System (OBSS) module that, starting from geometry information of a ship hull, described by a discrete model in a standard format, and the distribution of all weights onboard calculates the ship floating conditions (in draught, heel and trim).

Keywords: Algorithms, Computer applications, Equilibrium, Marine applications, Stability System.

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Authors: Ime R. Udotong, Justina I. R. Udotong, Ofonime U. M. John

Abstract:

Brass terminal, one of the several crude oil and petroleum products storage/handling facilities in the Niger Delta was built in the 1980s. Activities at this site, over the years, released crude oil into this 3 m-deep, 1500 m-long canal lying adjacent to the terminal with oil floating on it and its sediment heavily polluted. To ensure effective clean-up, three major activities were planned: site characterization, bioremediation pilot plant construction and testing and full-scale bioremediation of contaminated sediment / bank soil by land farming. The canal was delineated into 12 lots and each characterized, with reference to the floating oily phase, contaminated sediment and canal bank soil. As a result of site characterization, a pilot plant for on-site bioremediation was designed and a treatment basin constructed for carrying out pilot bioremediation test. Following a designed sampling protocol, samples from this pilot plant were collected for analysis at two laboratories as a quality assurance / quality control check. Results showed that Brass Canal upstream is contaminated with dark, thick and viscous oily film with characteristic hydrocarbon smell while downstream, thin oily film interspersed with water was observed. Sediments were observed to be dark with mixture of brownish sandy soil with TPH ranging from 17,800 mg/kg in Lot 1 to 88,500 mg/kg in Lot 12 samples. Brass Canal bank soil was observed to be sandy from ground surface to 3m, below ground surface (bgs) it was silty-sandy and brownish while subsurface soil (4-10m bgs) was sandy-clayey and whitish/grayish with typical hydrocarbon smell. Preliminary results obtained so far have been very promising but were proprietary. This project is considered, to the best of technical literature knowledge, the first large-scale on-site bioremediation project in the Niger Delta region, Nigeria.

Keywords: Bioremediation, Contaminated sediment, Land farming, Oily sludge, Oil Terminal.

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Authors: Y. J. Huang, J. D. Yu, B. W. Hong, C. H. Tai, T. C. Kuo

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In this paper, a multi-agent robot system is presented. The system consists of four robots. The developed robots are able to automatically enter and patrol a harmful environment, such as the building infected with virus or the factory with leaking hazardous gas. Further, every robot is able to perform obstacle avoidance and search for the victims. Several operation modes are designed: remote control, obstacle avoidance, automatic searching, and so on.

Keywords: autonomous robot, field programmable gate array, obstacle avoidance, ultrasonic sensor, wireless communication.

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Authors: Yngvar Berg, Omid Mirmotahari

Abstract:

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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Authors: Shujaat A. Khan, Ghulam Murtaza

Abstract:

This presentation narrates the comparative analysis of the dissolution data nimesulide microparticles prepared with ethylcellulose, hydroxypropyl methylcellulose, chitosan and Poly(D,L-lactide-co-glycolide) as polymers. The analysis of release profiles showed that the variations noted in the release behavior of nimesulide from various microparticulate formulations are due to the nature of used polymer. In addition, maximum retardation in the nimesulide release was observed with HPMC (floating particles). Thus HPMC miacroparticles may be preferably employed for sustained release dosage form development.

Keywords: Nimesulide, microparticles, ethylcellulose, hydroxypropyl methylcellulose, chitosan and Poly(D, L-lactide-coglycolide).

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Authors: Zdeňka Rendlová

Abstract:

This paper presents the mathematical description of the high-speed rotating system taking into account the influence of internal and external damping. The mathematical model is obtained by using the finite element method. The analyzed system is an automotive turbocharger understood as a rotor-bearing system. The circular cross-section shaft is equipped with one compressor wheel, one turbine wheel and is supported by two floating ring bearings. Based on the model, the dynamical analysis of a turbocharger is performed and stability conditions are evaluated.

Keywords: External damping, internal damping, journal bearing, stability, turbocharger.

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Authors: B. Rajesh Kamath, J. Sundara Rajan

Abstract:

Partial Discharge measurement is a very important means of assessing the integrity of insulation systems in a High Voltage apparatus. In compressed gas insulation systems, floating particles can initiate partial discharge activities which adversely affect the working of insulation. Partial Discharges below the inception voltage also plays a crucial in damaging the integrity of insulation over a period of time. This paper discusses the effect of loose and fixed Copper and Nichrome wire particles on the PD characteristics in SF6-N2 (10:90) gas mixtures at a pressure of 0.4MPa. The Partial Discharge statistical parameters and their correlation to the observed results are discussed.

Keywords: Gas Insulated transmission Line, Sulphur HexaFlouride, metallic Particles, Partial Discharge (PD), InceptionVoltage (Vi), Extinction Voltage (Ve), PD Statistical parameters.

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Authors: Jaouadi Ikram, Machhout Mohsen

Abstract:

The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process.

Keywords: QKD, BB84, protocol, cryptography, FPGA, key, security, communication.

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