Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4

Search results for: A. Zitouni

4 Effect of Spatially Correlated Disorder on Electronic Transport Properties of Aperiodic Superlattices (GaAs/AlxGa1-xAs)

Authors: F. Bendahma, S. Bentata, S. Cherid, A. Zitouni, S. Terkhi, T. Lantri, Y. Sefir, Z. F. Meghoufel

Abstract:

We examine the electronic transport properties in AlxGa1-xAs/GaAs superlattices. Using the transfer-matrix technique and the exact Airy function formalism, we investigate theoretically the effect of structural parameters on the electronic energy spectra of trimer thickness barrier (TTB). Our numerical calculations showed that the localization length of the states becomes more extended when the disorder is correlated (trimer case). We have also found that the resonant tunneling time (RTT) is of the order of several femtoseconds.

Keywords: Electronic transport properties, structural parameters, superlattice, transfer-matrix technique.

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3 A Generic and Extensible Spidergon NoC

Authors: Abdelkrim Zitouni, Mounir Zid, Sami Badrouchi, Rached Tourki

Abstract:

The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.

Keywords: Dynamic arbiter, Generic router, Spidergon NoC, SoC.

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2 Adaptive Motion Estimator Based on Variable Block Size Scheme

Authors: S. Dhahri, A. Zitouni, H. Chaouch, R. Tourki

Abstract:

This paper presents an adaptive motion estimator that can be dynamically reconfigured by the best algorithm depending on the variation of the video nature during the lifetime of an application under running. The 4 Step Search (4SS) and the Gradient Search (GS) algorithms are integrated in the estimator in order to be used in the case of rapid and slow video sequences respectively. The Full Search Block Matching (FSBM) algorithm has been also integrated in order to be used in the case of the video sequences which are not real time oriented. In order to efficiently reduce the computational cost while achieving better visual quality with low cost power, the proposed motion estimator is based on a Variable Block Size (VBS) scheme that uses only the 16x16, 16x8, 8x16 and 8x8 modes. Experimental results show that the adaptive motion estimator allows better results in term of Peak Signal to Noise Ratio (PSNR), computational cost, FPGA occupied area, and dissipated power relatively to the most popular variable block size schemes presented in the literature.

Keywords: H264, Configurable Motion Estimator, VariableBlock Size, PSNR, Dissipated power.

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1 Field-Programmable Gate Array Based Tester for Protective Relay

Authors: H. Bentarzi, A. Zitouni

Abstract:

The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: Amplifier class D, FPGA, protective relay, tester.

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