Search results for: MIPS

Authors: Bianca Schweiger, Lucile Bahnweg, Barbara Palm, Ute Steinfeld

Abstract:

The occurrence and removal of trace organic contaminants in the aquatic environment has become a focus of environmental concern. For the selective removal of carbamazepine from loaded waters molecularly imprinted polymers (MIPs) were synthesized with carbamazepine as template. Parameters varied were the type of monomer, crosslinker, and porogen, the ratio of starting materials, and the synthesis temperature. Best results were obtained with a template to crosslinker ratio of 1:20, toluene as porogen, and methacrylic acid (MAA) as monomer. MIPs were then capable to recover carbamazepine by 93% from a 10-5 M landfill leachate solution containing also caffeine and salicylic acid. By comparison, carbamazepine recoveries of 75% were achieved using a nonimprinted polymer (NIP) synthesized under the same conditions, but without template. In landfill leachate containing solutions carbamazepine was adsorbed by 93-96% compared with an uptake of 73% by activated carbon. The best solvent for desorption was acetonitrile, with which the amount of solvent necessary and dilution with water was tested. Selected MIPs were tested for their reusability and showed good results for at least five cycles. Adsorption isotherms were prepared with carbamazepine solutions in the concentration range of 0.01 M to 5*10-6 M. The heterogeneity index showed a more homogenous binding site distribution.

Keywords: Carbamazepine, landfill leachate, removal, reuse

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Authors: Rehab Abdullah Shendi

Abstract:

The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: Customisation, FPGA, MIPS, partial reconfiguration.

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