Run-Time Customisation of Soft-Core CPUs on Field Programmable Gate Array
Authors: Rehab Abdullah Shendi
The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1127944Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 916
 Koch, D., 2013. Partial Reconﬁguration on FPGAs: Architectures, Tools and Applications. New York: Springer.
 Beckhoff, C., Koch, D. & Torresen, J., 2012. Go ahead: A partial reconfiguration framework. Field-Programmable Custom Computing Machines (FCCM), 2012 IEEE 20th Annual International Symposium, pp. 37-44.
 Fritzell, A., 2013. A System for Fast Dynamic Partial Reconfiguration using GoAhead Design and Implementation. Master’s Thesis: University of Oslo.
 Koch, D., Beckhoff, C. & Torreson, J., 2010. Zero logic overhead integration of partially reconfigurable modules. Proceedings of the 23rd symposium on Integrated circuits and system design, pp. 103-108.
 Hauck, S., 1998. Configuration prefetch for single context reconfigurable coprocessors. In: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays. New York: ACM, pp. 65-74.
 Pittman, R. N., Lynch, N. L. & Forin, A., 2006. eMIPS, A Dynamically Extensible Processor, Redmond: Microsoft Research.
 Kulkarni, R., 2006. Disruptive Technology. Computing & Control Engineering Journal. vol. 17, no. 1, Feb.-Mar., pp. 32-35.
 Deschamps, Jean-Pierre, Sutter, Gustavo D., Cantó, Enrique "Guide to FPGA Implementation of Arithmetic Functions" Lecture Notes in Electrical Engineering, Volumen 149. Springer Netherlands 2012
 Kozyrakis, C. E. & Patterson, D. A., 2004. Scalable, vector processors for embedded systems. Micro, IEEE, 23(6), pp. 36-45.
 Kilts, S. (2007). Advanced FPGA design: architecture, implementation, and optimization. John Wiley & Sons.
 Minev, P. B. & Kukenska, V. S., 2007. Implemenation of Soft-core Processors in FPGAs. Gabrovo, International Scientific Conference.
 Gebotys, C. H., 2012. A network flow approach to memory bandwidth utilization in embedded DSP core processors. IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 10(4), pp. 390-398.
 Synopsys, 2010. SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family. (Online) Available at: http://news.synopsys.com/index.php?s=20295&item=123144 (Accessed 30 March 2015).
 Altera. (2011, Jan.) Nios II Custom Instruction User Guide. (Online). http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf
 S. Majzoub, H. Diab, "Mapping and Performance Analysis of Lookup Table Implementations on Reconfigurable Platform," IEEE/ACS International Conference on Computer Systems and Applications (AICCSA’07), Le Méridien Amman Hotel, Amman, Jordan, May 13-16, 2007 pp.513-520.
 Galuzzi, C. & Bertels, K., 2011. The Instruction-Set Extension Problem: A Survey. ACM Transactions on Reconfigurable Technology and Systems. article 18, 4(2).
 Wold, A., Koch, D. & Torresen, J., 2012. Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs. s.l., IEEE, pp. 50-55.
 Jo, J., 2013. 6 Basic Phases of Software Development Life Cycle (SDLC). (Online) Available at: http://www.techknol.net/2013/04/software-development-life-cycle.html (Accessed 15 August 2015).
 Elkateeb, A., 2011. A Processor Design Course Project: Creating Soft-Core MIPS Processor Using Step-by-Step Components' Integration Approach. International Journal of Information and Education Technology, 1(5), pp. 432-440.
 Fletcher, B., 2005. FPGA Embedded Processors Revealing True System Performance. In: Embedded Training Program Embedded Systems Conference.. (Online) Available at: http://www.xilinx.com/products/design_resources/proc_central/resource/ETP-367paper.pdf (Accessed 14 August 2015).
 Xilinx Inc, 2015. Spartan-6 FPGA Configuration User Guide. (Online) Available at: http://www.xilinx.com/support/documentation/user_guides/ug380.pdf (Accessed 11 August 2015).
 Xilinx, 2012. Partial Configuration User Guide. (Online) Available at: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf (Accessed 1 August 2015).
 Doulos.com, 2015. Simple Ram Model. (Online) Available at: https://www.doulos.com/knowhow/vhdl_designers_guide/models/simple_ram_model/ (Accessed 7 August 2015).
 OutputLogic.com, 2013. OutputLogic.com. (Online) Available at: http://outputlogic.com/ (Accessed 30 August 2015).
 Andersen, S. E., 2005. Bit Twiddling Hacks. (Online) Available at: http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetNaive (Accessed 31 August 2015).