Search results for: On-Chip interconnect

Authors: Kureshi Abdul Kadir, Mohd. Hasan

Abstract:

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as energy efficient and high speed interconnect for future FPGA routing architecture. All HSPICE simulations are carried out at operating frequency of 1GHz and it is found that mixed CNT bundle implemented in FPGAs as interconnect can potentially provide a substantial delay and energy reduction over traditional interconnects at 32nm process technology.

Keywords: CMOS, Copper Interconnect, Mixed CNT Bundle Interconnect, FPGAs.

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Authors: Shilpi Lavania

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As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: Guang Sun, Yong Li, Yuanyuan Zhang, Shijun Lin, Li Su, Depeng Jin, Lieguang zeng

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Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Keywords: Network on Chip (NoC), interconnect architecture, performance, area, Three Dimensional Integrate Circuit (3D IC).

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Authors: Jong-Bae Lee, Seongsoo Lee

Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: Local interconnect network, controller, transceiver, processor.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

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The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Kollarama Subramanyam, Nisha Kuruvilla, J. P. Raina

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Novel compact expressions for propagation constant (γ) of SWCNT and bundled SWCNTs interconnect, in terms of physical parameters such as length, operating frequency and diameter of CNTs is proposed in this work. These simplified expressions enable physical insight and accurate estimation of signal attenuation level and its phase change at any length for a particular frequency. The proposed expressions are validated against SPICE simulated results of lumped as well as distributed equivalent electrical RLC nets of CNT interconnect. These expressions also help us to evaluate the cut off frequencies of SWCNTs for different interconnect lengths.

Keywords: Attenuation constant, Bundled SWCNT, CNT interconnects, Propagation Constant.

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Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

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With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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Authors: Sunil Jadav, Rajeevan Chandel Munish Vashishath

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Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.

Keywords: Current Mode, Voltage Mode, VLSI Interconnect.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

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This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.

Keywords: Crosstalk, distributed RLC segments, On-Chip interconnect, output response, VLSI, noise peak, noise width.

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Authors: M. İskefiyeli, İ. Özçelik

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PROFIBUS (PROcess FIeld BUS) which is defined with international standarts (IEC61158, EN50170) is the most popular fieldbus, and provides a communication between industrial applications which are located in different control environment and location in manufacturing, process and building automation. Its communication speed is from 9.6 Kbps to 12 Mbps over distances from 100 to 1200 meters, and so it is to be often necessary to interconnect them in order to break these limits. Unfortunately this interconnection raises several issues and the solutions found so far are not very satisfactory. In this paper, we propose a new solution to interconnect PROFIBUS segments, which uses a wireless MAN based on the IEEE 802.16 standard as a backbone system. Also, the solution which is described a model for internetworking unit integrates the traffic generated by PROFIBUS segments into IEEE 802.16 wireless MAN using encapsulation technique.

Keywords: Internetworking Unit, PROFIBUS, WiMAX, WMAN, 802.16.

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Authors: Bhaskar M., Venkataramani B.

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In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, delay locked loop (DLL) along with 40mm metal 4 interconnects using the proposed surfing technique is implemented in UMC 180nm technology and their performances are studied through post layout simulations. From the study, it is observed that the proposed scheme permits 1.875 times higher data transmission rate compared to the single ended scheme whose maximum data transfer rate is 1.33 GB/s. The proposed scheme has the ability to receive the correct data even with stuck-at-faults in the complementary line.

Keywords: Controllable inverter pair, differential interconnect, serial link, surfing, wave pipelining.

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Authors: M. B. Limooei, Hadi Ebrahimifar, Sh. Hosseini

Abstract:

Protective coatings that resist oxide scale growth and decrease chromium evaporation are necessary to make stainless steel interconnect materials for long-term durable operation of solid oxide fuel cells (SOFCs). In this study a layer of cobalt was electroplated on the surface of AISI 441 ferritic stainless steel which is used in solid oxide fuel cells for interconnect applications. The oxidation behavior of coated substrates was studied as a function of time at operating conditions of SOFCs. Cyclic oxidation has been also tested at 800ºC for 100 cycles. Cobalt coating during isothermal oxidation caused to the oxide growth resistance by limiting the outward diffusion of Cr cation and the inward diffusion of oxygen anion. Results of cyclic oxidation exhibited that coated substrates demonstrate an excellent resistance against the spallation and cracking.

Keywords: Oxidation resistance, full cell, Cobalt coating, ferritic stainless steel.

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Authors: S. N. Hosseini, M. H. Enayati, F. Karimzadeh, N. M. Sammes

Abstract:

The synthesis of CuFe2O4 spinel powders by an optimized combustion-like process followed by calcination is described herein. The samples were characterized using X-ray diffraction (XRD), differential thermal analysis (TG/DTA), scanning electron microscopy (SEM), dilatometry and 4-probe DC methods. Different glycine to nitrate (G/N) ratios of 1 (fuel-deficient), 1.48 (stoichiometric) and 2 (fuel-rich) were employed. Calcining the asprepared powders at 800 and 1000°C for 5 hours showed that the G/N ratio of 2 results in the formation of the desired copper spinel single phase at both calcination temperatures. For G/N=1, formation of CuFe2O4 takes place in three steps. First, iron and copper nitrates decompose to iron oxide and pure copper. Then, copper transforms to copper oxide and finally, copper and iron oxides react with each other to form a copper ferrite spinel phase. The electrical conductivity and the coefficient of thermal expansion of the sintered pelletized samples were 2 S.cm-1 (800°C) and 11×10-6 °C-1 (25-800°C), respectively.

Keywords: SOFC interconnect coatings, Copper ferrite, Spinels, Electrical conductivity, Glycine–nitrate process.

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Authors: Shiyang Zhu, Guo-Qiang Lo, Dim-Lee Kwong

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Although silicon photonic devices provide a significantly larger bandwidth and dissipate a substantially less power than the electronic devices, they suffer from a large size due to the fundamental diffraction limit and the weak optical response of Si. A potential solution is to exploit Si plasmonics, which may not only miniaturize the photonic device far beyond the diffraction limit, but also enhance the optical response in Si due to the electromagnetic field confinement. In this paper, we discuss and summarize the recently developed metal-insulator-Si-insulator-metal nanoplasmonic waveguide as well as various passive and active plasmonic components based on this waveguide, including coupler, bend, power splitter, ring resonator, MZI, modulator, detector, etc. All these plasmonic components are CMOS compatible and could be integrated with electronic and conventional dielectric photonic devices on the same SOI chip. More potential plasmonic devices as well as plasmonic nanocircuits with complex functionalities are also addressed.

Keywords: Silicon nanoplasmonics, Silicon nanophotonics, Onchip integration, CMOS

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Authors: Imran Ihsan, Muhammad Abdul Qadir, Nadeem Iftikhar

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Mobile devices, which are progressively surrounded in our everyday life, have created a new paradigm where they interconnect, interact and collaborate with each other. This network can be used for flexible and secure coordinated sharing. On the other hand Grid computing provides dependable, consistent, pervasive, and inexpensive access to high-end computational capabilities. In this paper, efforts are made to map the concepts of Grid on Ad-Hoc networks because both exhibit similar kind of characteristics like Scalability, Dynamism and Heterogeneity. In this context we propose “Mobile Ad-Hoc Services Grid – MASGRID".

Keywords: Mobile Ad-Hoc Networks, Grid Computing, Resource Discovery, Routing

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Authors: Ki-Young Kim, Jae-Ho Lim, Deok-Min Kim, Seok-Yoon Kim

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Average current analysis checking the impact of current flow is very important to guarantee the reliability of semiconductor systems. As semiconductor process technologies improve, the coupling capacitance often become bigger than self capacitances. In this paper, we propose an analytic technique for analyzing average current on interconnects in multi-conductor structures. The proposed technique has shown to yield the acceptable errors compared to HSPICE results while providing computational efficiency.

Keywords: current moment, interconnect modeling, reliability analysis, worst-case switching

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Authors: Se-Jin Ko, Deok-Min Kim, Seok-Yoon Kim

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The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

Keywords: clock, clock-skew, temperature, thermal.

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Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

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Silicon photonics is merging as a unified platform for driving photonic based telecommunications and for local photonic based interconnect but it suffers from large footprint as compared with the nanoelectronics. Plasmonics is an attractive alternative for nanophotonics. In this work, two CMOS compatible plasmonic waveguide platforms are compared. One is the horizontal metal-insulator-Si-insulator-metal nanoplasmonic waveguide and the other is metal-insulator-Si hybrid plasmonic waveguide. Various passive and active photonic devices have been experimentally demonstrated based on these two plasmonic waveguide platforms.

Keywords: Plasmonics, on-chip integration, Silicon photonics.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

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The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the ¤Ç-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differential equations which accurately describe the behavior of the circuit. The effect of coupling capacitance between input and output and the short circuit current on these performance parameters are also incorporated in the proposed model. The estimated proposed delay and short circuit power dissipation are in very good agreement with the SPICE simulation with average relative error less than 6%.

Keywords: Delay, Inverter, Short Circuit Power, ¤Ç-Model, RLCInterconnect, VLSI

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Authors: Boudene Maamar, Xu Mai

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Optical Intersatellite Links (OISLs) are wireless communications using optical signals to interconnect satellites. It is expected to be the next generation wireless communication technology according to its inherent characteristics like: an increased bandwidth, a high data rate, a data transmission security, an immunity to interference, and an unregulated spectrum etc. Optical space links are the best choice for the classical communication schemes due to its distinctive properties; high frequency, small antenna diameter and lowest transmitted power, which are critical factors to define a space communication. This paper discusses the development of free space technology and analyses the parameters and factors to establish a reliable intersatellite links using an optical signal to exchange data between satellites.

Keywords: Optical intersatellite links, optical wireless communications, free space optical communications, next generation wireless communication.

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Authors: Abdelkrim Zitouni, Mounir Zid, Sami Badrouchi, Rached Tourki

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The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.

Keywords: Dynamic arbiter, Generic router, Spidergon NoC, SoC.

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Authors: Omer Mahmood, Selvakennedy Selvadurai

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“Web of Trust" is one of the recognized goals for Web 2.0. It aims to make it possible for the people to take responsibility for what they publish on the web, including organizations, businesses and individual users. These objectives, among others, drive most of the technologies and protocols recently standardized by the governing bodies. One of the great advantages of Web infrastructure is decentralization of publication. The primary motivation behind Web 2.0 is to assist the people to add contents for Collective Intelligence (CI) while providing mechanisms to link content with people for evaluations and accountability of information. Such structure of contents will interconnect users and contents so that users can use contents to find participants and vice versa. This paper proposes conceptual information storage and linking model, based on decentralized information structure, that links contents and people together. The model uses FOAF, Atom, RDF and RDFS and can be used as a blueprint to develop Web 2.0 applications for any e-domain. However, primary target for this paper is online trust evaluation domain. The proposed model targets to assist the individuals to establish “Web of Trust" in online trust domain.

Keywords: Web of Trust, Semantic Web, Electronic SocialNetworks, Information Management

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Authors: P.Ramanathan, P.T.Vanathi

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Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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Authors: Saeed Ghali, Azza Ahmed, Taha Mattar

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Solid Oxide Fuel Cell (SOFC) is a promising solution for the energy resources leakage. Ferritic stainless steel becomes a suitable candidate for the SOFCs interconnects due to the recent advancements. Different steel alloys were designed to satisfy the needed characteristics in SOFCs interconnect as conductivity, thermal expansion and corrosion resistance. Refractory elements were used as alloying elements to satisfy the needed properties. The oxidation behaviour of the developed alloys was studied where the samples were heated for long time period at the maximum operating temperature to simulate the real working conditions. The formed scale and oxidized surface were investigated by SEM. Microstructure examination was carried out for some selected steel grades. The effect of alloying elements on the behaviour of the proposed interconnects material and the performance during the working conditions of the cells are explored and discussed. Refractory metals alloying of chromium steel seems to satisfy the needed characteristics in metallic interconnects.

Keywords: SOFCs, Cr-steel, interconnects, oxidation.

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Authors: N. Aravantinos-Zafiris, M. M. Sigalas

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In this work we numerically examine structures which could confine light in nanometer areas. A system consisting of two silicon disks with in plane separation of a few tens of nanometers has been studied first. The normalized unitless effective mode volume, Veff, has been calculated for the two lowest whispering gallery mode resonances. The effective mode volume is reduced significantly as the gap between the disks decreases. In addition, the effect of the substrate is also studied. In that case, Veff of approximately the same value as the non-substrate case for a similar two disk system can be obtained by using disks almost twice as thick. We also numerically examine a structure consisting of a circular slot waveguide which is formed into a silicon disk resonator. We show that the proposed structure could have high Q resonances thus raising the belief that it is a very promising candidate for optical interconnects applications. The study includes several numerical calculations for all the geometric parameters of the structure. It also includes numerical simulations of the coupling between a waveguide and the proposed disk resonator leading to a very promising conclusion about its applicability.

Keywords: Disk resonators, field enhancement, optical interconnect, slot waveguides.

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Authors: C. Cruz, A. Breda

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The world is changing and, consequently, the young people need to acquire more sophisticated tools and skills to lead with the new societies’ challenges. In the curriculum of the Portuguese education system, in the profile of students leaving compulsory education, the critical thinking and creative thinking are pointed out as skills to be developed, as well as the capacity of interconnect different knowledge and applicate them in different contexts and learning areas. Unlike primary school teachers, teachers specialized in a specific area sometimes reveal more difficulties in developing interdisciplinary approaches in the classrooms and, despite the effort, the interdisciplinarity is not a common practice in schools. Statements like "Mathematics is everywhere" are unquestionable, however, some math teachers continue to develop an abstract teaching of mathematics devoid of any connection with reality. Good mathematical problems in real contexts are promising in the development of interdisciplinary pedagogical practices. However, these problems are often addressed by teachers in multidisciplinary rather than interdisciplinary contexts or are not addressed at all due several reasons, which range from insecurity in working on disciplinary domains with which they are not comfortable to a lack of pedagogical resources. In this study this issue is approached through a case study involving Mathematics teachers, which, in their professional development scope, attended a training aimed at stimulating interdisciplinary practices in real contexts, namely related to the COVID-19 pandemic.

Keywords: Interdisciplinarity, Mathematics, professional development, teacher training.

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Authors: Bassim Bachy, Joerg Franke

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In this study, a three dimensional numerical heat transfer model has been used to simulate the laser structuring of polymer substrate material in the Three-Dimensional Molded Interconnect Device (3D MID) which is used in the advanced multifunctional applications. A finite element method (FEM) transient thermal analysis is performed using APDL (ANSYS Parametric Design Language) provided by ANSYS. In this model, the effect of surface heat source was modeled with Gaussian distribution, also the effect of the mixed boundary conditions which consist of convection and radiation heat transfers have been considered in this analysis. The model provides a full description of the temperature distribution, as well as calculates the depth and the width of the groove upon material removal at different set of laser parameters such as laser power and laser speed. This study also includes the experimental procedure to study the effect of laser parameters on the depth and width of the removal groove metal as verification to the modeled results. Good agreement between the experimental and the model results is achieved for a wide range of laser powers. It is found that the quality of the laser structure process is affected by the laser scan speed and laser power. For a high laser structured quality, it is suggested to use laser with high speed and moderate to high laser power.

Keywords: Laser Structuring, Simulation, Finite element analysis, Thermal modeling.

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