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A Clock Skew Minimization Technique Considering Temperature Gradient
Abstract:The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1072505Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1223
 M. Cho, S. Ahmed, and D. Z. Pan, "TACO: temperature aware clock-tree optimization," in Proc. ICCAD'05, pp. 581-586, Nov. 2005.
 K, Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-Aware Computer Systems: Opportunities and Challenges," IEEE Micro, Vol. 23, No.6, pp. 52-61, Nov-Dec 2003.
 S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter Variation and Impact on Circuits and Microarchitectures," in Proc. DAC-40, pp. 338-342, Jun. 2003.
 K. Baneragee, A. H. Ajami, and M. Pedram, "Analysis and optimization of thermal issues in high-performance VLSI," in Proc. Int. Symp. on Physical Design, pp. 230-237, April 2001.
 O. Semenov, A. Vassighi, M. Sachdev, A. Kechavarzi, and C.F. Hawkins, "Burn-in temperature projections for deep sub-micron technologies," in Proc. ITC, pp. 719-226, 2003.
 International Technology Roadmap for Semiconductors (ITRS) : Interconnect, 2008.