Accurate Crosstalk Analysis for RLC On-Chip VLSI Interconnect

Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.

Keywords: Crosstalk, distributed RLC segments, On-Chip interconnect, output response, VLSI, noise peak, noise width.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1060547

References:

[1] Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1997.
[2] Shepard K L, Narayanan V. "Noise in deep submicron digital design". Proc. IEEE Int. Conference on Computer Aided Design, pp. 524-531, 1996.
[3] Vittal A, and M. Marek-Sadowska, "Crosstalk reduction for VLSI", IEEE Transactions on Computer-Aided Design, Vol. 16, pp. 1817-1824, 1997.
[4] Kahng A B, Muddu S, Vidhani D. "Noise and delay uncertainty studies for coupled RC interconnections". IEEE Int. ASIC/SOC Conf., pp. 3-8, 1999.
[5] Nakagawa S, Sylvester D M, McBride J, Oh S Y. "On-Chip crosstalk noise model for deep sub micrometer ULSI interconnect". Hewlett Packard Journal, Vol. 49, pp.39-45, 1998.
[6] Cong J, Pan D Z, Srinavas P V. "Improved crosstalk modeling for noise constrained interconnect optimization". Proceedings of ASP/DAC, pp. 373-378, 2001.
[7] Becer M R, Blaauw D, Zolotov V, Panda R, Hajj I N. "Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model", Design, Automation and Test in Europe Conference, pp. 456-464, 2002.
[8] Sayil S, Rudrapati M. "Accurate prediction of crosstalk for RC Interconnect". Turk J. Elec. Eng. and Comp Science, Vol.17, No.1, 2009, pp. 55-67.
[9] Tang K T, Friedman E G. "Peak crosstalk noise estimation in CMOS VLSI circuits". in Proc. IEEE Int. Conf. Electron. Circuits Syst., pp. 1539-1542, 1999.
[10] Chen J, He L. "A decoupling method for analysis of coupled RLC interconnects". in Proc. ACM Great Lakes Symp. VLSI, pp.41-46,2002.
[11] Jin W, Yoon S, Kim J. "Experimental characterization and modeling of transmission line effects for high speed VLSI circuit interconnects". Inst. Electron. Informat. Commun. Eng. Trans. Electron., vol.83, no. 5, pp. 728-735, May 2000.
[12] Zhang J, Friedman E G. "Crosstalk noise model for shielded interconnects in VLSI based circuits," in Proc. IEEE Int. SOC Conf., pp.243-244, 2003.
[13] Levy R, Blaauw D, Braca G, Dasgupta A, Grinshpon A, Oh C, Orshav B, Sirichotiyakul S, Zolotov V. "Clarinet: A noise analysis tool for deep submicron design". in Proc. Int. Conf. Computer-Aided Design, pp. 587- 594, Nov. 2002.
[14] Qian J, Pullela S, Pillage L T. "Modeling the effective capacitance for the RC interconnect of CMOS gates". IEEE Transactions on Computer- Aided Design, Vol. 13, pp. 1526-1535, 1994.
[15] Pillage L T, and Rohrer R A. "Asymptotic Waveform Evaluation for Timing Analysis". IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, pp. 352 - 366, 1990.
[16] Acar E, Odabasioglu A, Celik M, and Pileggi L. "S2p: a stable 2- pole RC delay and coupling noise metric IC interconnects". Proceedings 9th Great Lakes Symposium on VLSI, pp. 60-63, 1999.
[17] Kausik B K, Sarkar S, Agarwal R P, Joshi R C, "An analytical approach to dynamic crosstalk in coupled interconnects". Microelectronics journal, 41 (2010), pp. 85-92.
[18] Lorival J E, Deschacht D. "RLC Interconnect crosstalk waveform evaluation". 2007 IEEE international Symposium on Integrated Circuits (ISIC 2007), pp. 544-547,2007.
[19] Kim T, Kim D, Lee J, Eo Y. "Compact models for signal transient and crosstalk noise of coupled RLC interconnect lines with ramp input". 4th IEEE International Symposium on electronic design, test and applications, pp. 205-209, 2008.
[20] Roy S, Dounavis A. "Closed form delay and crosstalk models for RLC on-chip interconnects using a matrix rational approximations". IEEE transactions on Computer Aided Design of integrated circuits and systems, vol. 28, issue. 10, pp. 1481-1492, October, 2009.