@article{(Open Science Index):https://publications.waset.org/pdf/10001108,
	  title     = {A Superior Delay Estimation Model for VLSI Interconnect in Current Mode Signaling},
	  author    = {Sunil Jadav and  Rajeevan Chandel Munish Vashishath},
	  country	= {},
	  institution	= {},
	  abstract     = {Today’s VLSI networks demands for high speed. And
in this work the compact form mathematical model for current mode
signalling in VLSI interconnects is presented.RLC interconnect line
is modelled using characteristic impedance of transmission line and
inductive effect. The on-chip inductance effect is dominant at lower
technology node is emulated into an equivalent resistance. First order
transfer function is designed using finite difference equation, Laplace
transform and by applying the boundary conditions at the source and
load termination. It has been observed that the dominant pole
determines system response and delay in the proposed model. The
novel proposed current mode model shows superior performance as
compared to voltage mode signalling. Analysis shows that current
mode signalling in VLSI interconnects provides 2.8 times better
delay performance than voltage mode. Secondly the damping factor
of a lumped RLC circuit is shown to be a useful figure of merit.
},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {9},
	  number    = {2},
	  year      = {2015},
	  pages     = {492 - 497},
	  ee        = {https://publications.waset.org/pdf/10001108},
	  url   	= {https://publications.waset.org/vol/98},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 98, 2015},
	}