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Explicit Delay and Power Estimation Method for CMOS Inverter Driving on-Chip RLC Interconnect Load
Abstract:The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the ¤Ç-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differential equations which accurately describe the behavior of the circuit. The effect of coupling capacitance between input and output and the short circuit current on these performance parameters are also incorporated in the proposed model. The estimated proposed delay and short circuit power dissipation are in very good agreement with the SPICE simulation with average relative error less than 6%.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1333853Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1463
 J. R. Burns, "Switching Response of Complementary-Symmetry MOS transistor logic circuits", RCA Rev. Vol. 25, pp. 627-661, Dec. 1964.
 N. Hedestierna and K. O. Jeppson, "CMOS circuit speed and buffer optimization", IEEE Trans. On Computer-Aided Design, Vol. CAD- 6, no. 2, pp. 270-280, Mar. 1987.
 T. Sakurai and A.R. Newton, "Alpha-power Law MOSFET Model and its applications to CMOS Inverter Delay and Other Formulas", IEEE j. Solid-state circuits, vol. 25, no.2, pp. 584-594, April 1990.
 T. Sakurai, A. R. Newton, "Delay analysis of series-connected MOSFET circuits", IEEE J. Solid-State circuits, vol. 26, pp. 122-131, Feb. 1991.
 S. H. K. Embabi, R. Damdaran, "Delay Models for CMOS, BiCMOS, BiNMOS circuits and their applications for timing simulations", IEEE trans. Computer-Aided Design, vol. 13, pp. 1132- 1142, Sept. 1994.
 L. Bisdounis, S. Nikolaidis and O. Koufopavlou, "Analytical Transient Response and Propagation Delay Evaluation of the CMOS inverter for short-channel Devices", IEEE j. Solid-state Circuits, vol. 33, no. 2, pp. 302-306, February 1998.
 V. Adler and E. G. Friedman, "Delay and Power Expressions for a CMOS Inverter driving a Resistive-Capacitive Load", Proc. of IEEE Int. Symp. On Circuits and systems (ISCAS), pp. 101-104, 1996.
 J. Qian, S. Pullela and L. Pillage, "Modeling the Effective Capacitance for the RC interconnect of CMOS gates", IEEE trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
 F. Dartu, N. Menezes and L. T. Pileggi, "Performance Computation for Pre-characterized CMOS gates with RC loads", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 5, pp. 544-553, May 1996.
 Florentin Dartu, Noel Menezes, Jessica Qian, and Lawrence T. Pillage," A Gate-Delay model for High-Speed CMOS circuits", Proc. ACM/IEEE Design Automation Conference, pp. 576-580, 1994.
 A. Hirata, H. Onodera and K. Tamaru, "Estimation of Short-circuit power dissipation for static CMOS gates driving a CRC ¤Ç Load", Proc. International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 279-290, 1997.
 T. Sakurai, "Approximation of Wiring Delay in MOSFET LSI", IEEE J. Solid-state Circuits, vol. SC-18, pp. 418-426, Aug, 1983.
 S. Nikolaidis, A. Chatzigeorgiou and E. D. Kyriakis-Bitzaros, "Delay and Power Estimation for a CMOS Inverter driving RC interconnect Loads", vol 6, pp. 368-371, Jun 1998.
 Lakshmi K. Vakati, Janet Wang, "A new multi-ramp driver model with RLC Interconnect Load", Proc. International Symposium on Physical Design, vol. 5, pp. 269-272, May 2004.
 Guoqing Chen and Eby G. Friedman, "Effective Capacitance of RLC loads for estimating Short-Circuit Power", Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2006), no 4, 2006.