Skin Effect: A Natural Phenomenon for Minimization of Ground Bounce in VLSI RC Interconnect
Authors: Shilpi Lavania
Abstract:
As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.
Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1091110
Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3147References:
[1] D. A. Priore, "Inductance on Silicon for Sub-Micron CMOS VLSI,” in Proc. IEEE Symp. On VLSI Circuits, pp. 17-18, May (1993).
[2] M. P. May, A. Taflove, and J. Baron, "FD-TD Modeling of Digital Signal Propagation in 3-D circuits with Passive and Active Loads”, IEEE Trans. Microwave Theory Tech., Vol. 42, pp. 1514-1523, Aug. (1994).
[3] S. Mei, C. Amin and Y. I. Ismail, "Efficient Model Order Reduction Including Skin Effect”, Proc. IEEE, pp. 232-237, June (2003).
[4] H. A. Wheeler, "Formulas for the Skin-Effect,” Proc. of Institute of Radio Engineers, Vol.30, pp.412–424, Sept (1942).
[5] B. Krauter and S. Mehrotra, "Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Inter-connect Timing Analysis”, Proc. DAC, pp.303–308, (1998)
[6] D. B. Kuznetsov and J. E. Schutt-Aine, "Optimal Transient Simulation of Transmission Lines”, IEEE Trans. CAS, Vol.43, Issue.2, pp.110–121, Feb (1996).
[7] A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein, and Phillip J. Restle, "On-Chip Wiring Design Challenges for Gigahertz Operation,” Proc. of IEEE, Vol.89, Issue.4, pp.529–555, Apr (2001).
[8] A. Tsuchiya, M.Hashimoto and H.Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction”, Proc. of IEEE, pp. 691-696, Jan (2004).
[9] V. Maheshwari, S. Lavania, R. Kar, D. Mandal and A. K. Bhattacharjee, "Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect”, Journal of VLSI Design Tools & Technology,Volume 1, Issue 1, (2011).
[10] V. Maheshwari, S. Lavania, D. Sengupta, R. Kar, D. Mandal, A. K. Bhattacharjee, "An Explicit Crosstalk Aware Delay Modelling For On-Chip VLSI RLC Interconnect With Skin Effect” Journal of Electronic Devices, Frans, Vol.10, pp.499-505,(2011).
[11] S. Lavania and V. Maheshwari, "An Explicit Crosstalk Aware Delay Modelling for On-Chip RLC Interconnect for Ramp Input with Skin Effect” International Journal Of Engineering and Research Applications,Vol.1, Issue 4, pp.1352-1359, (2011).
[12] Skin Effect Douglas Brooks, Ultracad Design, Inc. Avaliable at http://www.ultracad.com, (online 2012).
[13] S. Lavania and S. K. Sharma, "Skin Effect in High Speed VLSI On-chip Interconnects”, International Conference on VLSI, Communication & Networks, Proc. V-CAN, (2011).
[14] Technical Report on "Understanding & Minimizing Ground Bounce”, Document No. AN-640, Fairchild Semiconductor, Available at www.fairchildsemi.com/an/AN/AN-640, Revised on Feb (2003).
[15] P. Heydari and M. Pedram, "Ground Bounce in Digital VLSI Circuits”, IEEE Trans. On VLSI Systems, Vol.11, Issue.2, pp.180 – 193, (2003).
[16] S. R. Vemuru, "Accurate Simultaneous Switching Noise Estimation Including Velocity-Saturation Effects”, IEEE Trans. On Comp., Package and Manufacturing. Technol. - Part B, Vol.19, Issue.2, May (1996).
[17] S. Jou, W. Cheng and Y. Lin, "Simultaneous Switching Noise Analysis and Low Bouncing Design”, IEEE Custom Integrated Circuit Conference, pp. 25.5.1-25.5.4, May (1998).
[18] H. Cha and O Kwon, "A New Analytic Model of Simultaneous Switching Noise in CMOS Systems”, IEEE Proc. Electronic. Comp. and Technology Conference, pp. 615-621, May (1998).