Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 97

Search results for: Inverter

97 Analysis of a PWM Boost Inverter for Solar Home Application

Authors: Rafia Akhter, Aminul Hoque

Abstract:

Solar Cells are destined to supply electric energy beginning from primary resources. It can charge a battery up to 12V dc. For residential use an inverter for 12V dc to 220Vac conversion is desired. For this a static DC-AC converter is necessarily inserted between the solar cells and the distribution network. This paper describes a new P.W.M. strategy for a voltage source inverter. This modulation strategy reduces the energy losses and harmonics in the P.W.M. voltage source inverter. This technique allows the P.W.M. voltage source inverter to become a new feasible solution for solar home application.

Keywords: Boost Inverter, inverter, duty cycle, PWM

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96 Contribution to Improving the DFIG Control Using a Multi-Level Inverter

Authors: Imane El Karaoui, Mohammed Maaroufi, Hamid Chaikhy

Abstract:

Doubly Fed Induction Generator (DFIG) is one of the most reliable wind generator. Major problem in wind power generation is to generate Sinusoidal signal with very low THD on variable speed caused by inverter two levels used. This paper presents a multi-level inverter whose objective is to reduce the THD and the dimensions of the output filter. This work proposes a three-level NPC-type inverter, the results simulation are presented demonstrating the efficiency of the proposed inverter.

Keywords: DFIG, multilevel inverter, NPC inverter , THD, Induction machine.

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95 A Literature Assessment of Multi-Level Inverters

Authors: P. Kiruthika, K. Ramani

Abstract:

Multi-Level Inverter technology has been developed in the area of high-power medium-voltage energy scheme, because of their advantages such as devices of lower rating can be used thereby enabling the schemes to be used for high voltage applications. Reduced Total Harmonic Distortion (THD).Since the dv/dt is low; the Electromagnetic Interference from the scheme is low. To avoid the switching losses Lower switching frequencies can be used. In this paper present a survey of various topologies, control strategy and modulation techniques used by these inverters. Here the regenerative and superior topologies are also discussed.

Keywords: Cascaded H-bridge Multi-Level Inverter, Diode Clamped Multi-Level Inverter, Flying Capacitors Multi- Level Inverter, Multi-Level Inverter, Total Harmonic Distortion.

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94 MPC of Single Phase Inverter for PV System

Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive (UI) single phase inverter (SPI) for a photovoltaic (PV) system at residential/distribution level. The proposed model uses single-phase phase locked loop (PLL) to synchronize SPI with the grid and performs MPC control in a dq reference frame. SPI model consists of boost converter (BC), maximum power point tracking (MPPT) control, and a full bridge (FB) voltage source inverter (VSI). No PI regulators to tune and carrier and modulating waves are required to produce switching sequence. Instead, the operational model of VSI is used to synthesize sinusoidal current and track the reference. Model is validated using a three kW PV system at the input of UI-SPI in Matlab/Simulink. Implementation and results demonstrate simplicity and accuracy, as well as reliability of the model.

Keywords: Matlab/Simulink, Model Predictive Control, Phase Locked Loop, Single Phase Inverter, Voltage Source Inverter.

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93 A Topology for High Voltage Gain Half-Bridge Z-Source Inverter with Low Voltage Stress on Capacitors

Authors: M. Nageswara Rao

Abstract:

In this paper, a topology for high voltage gain half-bridge z-source inverter with low voltage stress on capacitors is proposed. The proposed inverter has only one impedance network. It can generate symmetric and asymmetric voltages with different magnitudes during both half-cycles. By selecting the duty cycle it can also produce conventional half-bridge inverter characteristics. It is used in special applications like, electrochemical and electro plating applications. Calculations of voltage ripple of capacitors, capacitors voltage stress inductors current ripple are presented. The proposed topology is simulated using PSCAD software and the simulated values are compared with the theoretical values.

Keywords: Half-bridge inverter, impedance network-source inverter, high voltage gain inverter, power system computer aided design.

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92 Uniform Overlapped Multi-Carrier PWM for a Six-Level Diode Clamped Inverter

Authors: S.Srinivas

Abstract:

Multi-level voltage source inverters offer several advantages such as; derivation of a refined output voltage with reduced total harmonic distortion (THD), reduction of voltage ratings of the power semiconductor switching devices and also the reduced electro-magnetic-interference problems etc. In this paper, new carrier-overlapped phase-disposition or sub-harmonic sinusoidal pulse width modulation (CO-PD-SPWM) and also the carrieroverlapped phase-disposition space vector modulation (CO-PDSVPWM) schemes for a six-level diode-clamped inverter topology are proposed. The principle of the proposed PWM schemes is similar to the conventional PD-PWM with a little deviation from it in the sense that the triangular carriers are all overlapped. The overlapping of the triangular carriers on one hand results in an increased number of switchings, on the other hand this facilitates an improved spectral performance of the output voltage. It is demonstrated through simulation studies that the six-level diode-clamped inverter with the use of CO-PD-SPWM and CO-PD-SVPWM proposed in this paper is capable of generating multiple levels in its output voltage. The advantages of the proposed PWM schemes can be derived to benefit, especially at lower modulation indices of the inverter and hence this aspect of the proposed PWM schemes can be well exploited in high power applications requiring low speeds of operation of the drive.

Keywords: Diode clamped inverter, Pulse width modulation, Six level inverter, carrier based PWM.

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91 A Thirteen-Level Asymmetrical Cascaded H-Bridge Single Phase Inverter

Authors: P. Varalaxmi, A. Kirubakaran

Abstract:

This paper presents a thirteen-level asymmetrical cascaded H-bridge single phase inverter. In this configuration, the desired output voltage level is achieved by connecting the DC sources in different combinations by triggering the switches. The modes of operation are explained well for positive level generations. Moreover, a comparison is made with conventional topologies of diode clamped, flying capacitors and cascaded-H-bridge and some recently proposed topologies to show the significance of the proposed topology in terms of reduced part counts. The simulation work has been carried out in MATLAB/Simulink environment. The experimental work is also carried out for lower rating to verify the performance and feasibility of the proposed topology. Further the results are presented for different loading conditions.

Keywords: Multilevel inverter, pulse width modulation, total harmonic distortion, THD.

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90 Precision Control of Single-Phase PWM Inverter Using M68HC11E Microcontroller

Authors: Khaled A. Madi

Abstract:

Induction motors are being used in greater numbers throughout a wide variety of industrial and commercial applications because it provides many benefits and reliable device to convert the electrical energy into mechanical motion. In some application it-s desired to control the speed of the induction motor. Because of the physics of the induction motor the preferred method of controlling its speed is to vary the frequency of the AC voltage driving the motor. In recent years, with the microcontroller incorporated into an appliance it becomes possible to use it to generate the variable frequency AC voltage to control the speed of the induction motor. This study investigates the microcontroller based variable frequency power inverter. the microcontroller is provide the variable frequency pulse width modulation (PWM) signal that control the applied voltage on the gate drive, which is provides the required PWM frequency with less harmonics at the output of the power inverter. The fully controlled bridge voltage source inverter has been implemented with semiconductors power devices isolated gate bipolar transistor (IGBT), and the PWM technique has been employed in this inverter to supply the motor with AC voltage. The proposed drive system for three & single phase power inverter is simulated using Matlab/Simulink. The Matlab Simulation Results for the proposed system were achieved with different SPWM. From the result a stable variable frequency inverter over wide range has been obtained and a good agreement has been found between the simulation and hardware of a microcontroller based single phase inverter.

Keywords: Power, inverter, PWM, microcontroller.

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89 Three Phase PWM Inverter for Low Rating Energy Efficient Systems

Authors: Nelson K. Lujara

Abstract:

The paper presents a practical three-phase PWM inverter suitable for low voltage, low rating energy efficient systems. The work in the paper is conducted with the view to establishing the significance of the loss contribution from the PWM inverter in the determination of the complete losses of a photovoltaic (PV) arraypowered induction motor drive water pumping system. Losses investigated include; conduction and switching loss of the devices and gate drive losses. It is found that the PWM inverter operates at a reasonable variable efficiency that does not fall below 92% depending on the load. The results between the simulated and experimental results for the system with or without a maximum power tracker (MPT) compares very well, within an acceptable range of 2% margin.

Keywords: Energy, Inverter, Losses, Photovoltaic.

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88 Inverter Based Gain-Boosting Fully Differential CMOS Amplifier

Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter.

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87 Compensation Method Eliminating Voltage Distortions in PWM Inverter

Authors: H. Sediki, S. Djennoune

Abstract:

The switching lag-time and the voltage drop across the power devices cause serious waveform distortions and fundamental voltage drop in pulse width-modulated inverter output. These phenomenons are conspicuous when both the output frequency and voltage are low. To estimate the output voltage from the PWM reference signal it is essential to take account of these imperfections and to correct them. In this paper, on-line compensation method is presented. It needs three simple blocs to add at the ideal reference voltages. This method does not require any additional hardware circuit and off- line experimental measurement. The paper includes experimental results to demonstrate the validity of the proposed method. It is applied, finally, in case of indirect vector controlled induction machine and implemented using dSpace card.

Keywords: Dead time, field-oriented control, Induction motor, PWM inverter, voltage drop.

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86 A Novel Approach of Multilevel Inverter with Reduced Power Electronics Devices

Authors: M. Jagabar Sathik, K. Ramani

Abstract:

In this paper family of multilevel inverter topology with reduced number of power switches is presented. The proposed inverter can generate both even and odd level. The proposed topology is suitable for symmetric structure. The proposed symmetric inverter results in reduction of power switches, power diode and gate driver circuits and also it may further minimize the installation area and cost. To prove the superiority of proposed topology is compared with conventional topologies. The performance of this symmetric multilevel inverter has been tested by computer based simulation and prototype based experimental setup for nine-level inverter is developed and results are verified.

Keywords: Cascaded H- Bridge (CHB), Multilevel Inverter (MLI), Nearest Level Modulation (NLM), Total Harmonic Distortion (THD).

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85 Fuzzy Logic Based Cascaded H-Bridge Eleven Level Inverter for Photovoltaic System Using Sinusoidal Pulse Width Modulation Technique

Authors: M. S. Sivagamasundari, P. Melba Mary

Abstract:

Multilevel inverter is a promising inverter topology for high voltage and high power applications. This inverter synthesizes several different levels of DC voltages to produce a stepped AC output that approaches the pure sine waveform. The three different topologies, diode-clamped inverter, capacitor-clamped inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each PV array can act as a separate dc source for each h-bridge module. This research especially focus on photovoltaic power source as input to the system and shows the potential of a Single Phase Cascaded H-bridge Eleven level inverter governed by the fuzzy logic controller to improve the power quality by reducing the total harmonic distortion at the output voltage. Hence the efficiency of the system will be improved. Simulation using MATLAB/SIMULINK has been done to verify the performance of cascaded h-bridge eleven level inverter using sinusoidal pulse width modulation technique. The simulated output shows very favorable result.

Keywords: Multilevel inverter, Cascaded H-Bridge multilevel inverter, Total Harmonic Distortion, Photovoltaic cell, Sinusoidal pulse width modulation.

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84 Stability of Electrical Drives Supplied by a Three Level Inverter

Authors: M. S. Kelaiaia, H. Labar, S. Kelaiaia, T. Mesbah

Abstract:

The development of the power electronics has allowed increasing the precision and reliability of the electrical devices, thanks to the adjustable inverters, as the Pulse Wide Modulation (PWM) applied to the three level inverters, which is the object of this study. The authors treat the relation between the law order adopted for a given system and the oscillations of the electrical and mechanical parameters of which the tolerance depends on the process with which they are integrated (paper factory, lifting of the heavy loads, etc.).Thus, the best choice of the regulation indexes allows us to achieve stability and safety training without investment (management of existing equipment). The optimal behavior of any electric device can be achieved by the minimization of the stored electrical and mechanical energy.

Keywords: Multi level inverter, PWM, Harmonics, oscillation, control.

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83 Implementation and Comparison between Two Algorithms of Three-Level Neutral Point Clamped Voltage Source Inverter

Authors: K. Benamrane, T. Abdelkrim, T. Benslimane, Aeh. Benkhelifa, B. Bezza

Abstract:

This paper presents a comparison between two Pulse Width Modulation (PWM) algorithms applied to a three-level Neutral Point Clamped (NPC) Voltage Source Inverter (VSI). The first algorithm applied is the triangular-sinusoidal strategy; the second is the Space Vector Pulse Width Modulation (SVPWM) strategy. In the first part, we present a topology of three-level NCP VSI. After that, we develop the two PWM strategies to control this converter. At the end the experimental results are presented.

Keywords: Multilevel inverter, Space vector pulse width modulation (SVPWM), triangular-sinusoidal strategy.

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82 Stability of Electrical Motor Supplied by a Five Level Inverter

Authors: Kelaiaia Mounia Samira, Labar Hocine, Bounaya Kamel, Kelaiaia Samia

Abstract:

The development of the power electronics has allowed increasing the precision and reliability of the electrical trainings, thanks to the adjustable inverters, as the Pulse Wide Modulation (PWM) five level inverters, which is the object of study in this article.The authors treat the relation between the law order adopted for a given system and the oscillations of the electrical and mechanical parameters of which the tolerance depends on the process with which they are integrated (paper factory, lifting of the heavy loads, etc.).Thus the best choice of the regulation indexes allows us to achieve stability and safety training without investment (management of existing equipment).

Keywords: multi level inverter, PWM, Harmonics, oscillation, control

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81 Recent Advances in Pulse Width Modulation Techniques and Multilevel Inverters

Authors: Satish Kumar Peddapelli

Abstract:

This paper presents advances in pulse width modulation techniques which refers to a method of carrying information on train of pulses and the information be encoded in the width of pulses. Pulse Width Modulation is used to control the inverter output voltage. This is done by exercising the control within the inverter itself by adjusting the ON and OFF periods of inverter. By fixing the DC input voltage we get AC output voltage. In variable speed AC motors the AC output voltage from a constant DC voltage is obtained by using inverter. Recent developments in power electronics and semiconductor technology have lead improvements in power electronic systems. Hence, different circuit configurations namely multilevel inverters have became popular and considerable interest by researcher are given on them. A fast space-vector pulse width modulation (SVPWM) method for five-level inverter is also discussed. In this method, the space vector diagram of the five-level inverter is decomposed into six space vector diagrams of three-level inverters. In turn, each of these six space vector diagrams of three-level inverter is decomposed into six space vector diagrams of two-level inverters. After decomposition, all the remaining necessary procedures for the three-level SVPWM are done like conventional two-level inverter. The proposed method reduces the algorithm complexity and the execution time. It can be applied to the multilevel inverters above the five-level also. The experimental setup for three-level diode-clamped inverter is developed using TMS320LF2407 DSP controller and the experimental results are analyzed.

Keywords: Five-level inverter, Space vector pulse wide modulation, diode clamped inverter.

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80 Direct Power Control Strategies for Multilevel Inverter Based Custom Power Devices

Authors: S. Venkateshwarlu, B. P. Muni, A. D. Rajkumar, J. Praveen

Abstract:

Custom power is a technology driven product and service solution which embraces a family devices such as Dynamic Voltage Restorer (DVR), Distributed Shunt Compensator (DSTATCOM), Solid State Breaker (SSB) etc which will provide power quality functions at distribution voltages. The rapid response of these devices enables them to operate in real time, providing continuous and dynamic control of the supply including voltage and reactive power regulation, harmonic reduction and elimination of voltage dips. This paper presents the benefits of multilevel inverters when they are used for DPC based custom power devices. Power flow control mechanism, salient features, advantages and disadvantages of direct power control (DPC) using lookup table, SVM, predictive voltage vector and hybrid DPC strategies are discussed in this paper. Simulation results of three level inverter based STATCOM, harmonic analysis of multi level inverters are presented at the end.

Keywords: DPC, DPC-SVM, Dynamic voltage restorer, DSTATCOM, Multilevel inverter, PWM Converter, PDPC, VF-DPC.

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79 Explicit Delay and Power Estimation Method for CMOS Inverter Driving on-Chip RLC Interconnect Load

Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the ¤Ç-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differential equations which accurately describe the behavior of the circuit. The effect of coupling capacitance between input and output and the short circuit current on these performance parameters are also incorporated in the proposed model. The estimated proposed delay and short circuit power dissipation are in very good agreement with the SPICE simulation with average relative error less than 6%.

Keywords: Delay, Inverter, Short Circuit Power, ¤Ç-Model, RLCInterconnect, VLSI

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78 Elimination of Low Order Harmonics in Multilevel Inverter Using Nature-Inspired Metaheuristic Algorithm

Authors: N. Ould Cherchali, A. Tlemçani, M. S. Boucherit, A. Morsli

Abstract:

Nature-inspired metaheuristic algorithms, particularly those founded on swarm intelligence, have attracted much attention over the past decade. Firefly algorithm has appeared in approximately seven years ago, its literature has enlarged considerably with different applications. It is inspired by the behavior of fireflies. The aim of this paper is the application of firefly algorithm for solving a nonlinear algebraic system. This resolution is needed to study the Selective Harmonic Eliminated Pulse Width Modulation strategy (SHEPWM) to eliminate the low order harmonics; results have been applied on multilevel inverters. The final results from simulations indicate the elimination of the low order harmonics as desired. Finally, experimental results are presented to confirm the simulation results and validate the efficaciousness of the proposed approach.

Keywords: Firefly algorithm, metaheuristic algorithm, multilelvel inverter, SHEPWM.

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77 Lower Order Harmonics Minimisation in CHB Inverter Using GA and Decomposition by WT

Authors: V. Joshi Manohar, P. Sujatha, K. S. R. Anjaneyulu

Abstract:

Nowadays Multilevel inverters are widely using in various applications. Modulation strategy at fundamental switching frequency like, SHEPWM is prominent technique to eliminate lower order of harmonics with less switching losses and better harmonic profile. The equations which are formed by SHE are highly nonlinear transcendental in nature, there may exist single, multiple or even no solutions for a particular MI. However, some loads such as electrical drives, it is required to operate in whole range of MI. In order to solve SHE equations for whole range of MI, intelligent techniques are well suited to solve equations so as to produce lest %THDV. Hence, this paper uses Continuous genetic algorithm for minimising harmonics. This paper also presents wavelet based analysis of harmonics. The developed algorithm is simulated and %THD from FFT analysis and Wavelet analysis are compared. MATLAB programming environment and SIMULINK models are used whenever necessary.

Keywords: Cascade H-Bridge Inverter (CHB), Continuous Genetic Algorithm (C-GA), Selective Harmonic Elimination Pulse Width Modulation (SHEPWM), Total Harmonic Distortion (%THDv), Wavelet Transform (WT).

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76 Sensorless Backstepping Control Using an Adaptive Luenberger Observer with Three Levels NPC Inverter

Authors: A. Bennassar, A. Abbou, M. Akherraz, M. Barara

Abstract:

In this paper, we propose a sensorless backstepping control of induction motor (IM) associated with three levels neutral clamped (NPC) inverter. First, the backstepping approach is designed to steer the flux and speed variables to theirs references and to compensate the uncertainties. A Lyapunov theory is used and it demonstrates that the dynamic trajectories tracking are asymptotically stable. Second, we estimate the rotor flux and speed by using the adaptive Luenberger observer (ALO). Simulation results are provided to illustrate the performance of the proposed approach in high and low speeds and load torque disturbance.

Keywords: Sensorless backstepping, IM, Three levels NPC inverter, Lyapunov theory, ALO.

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75 Harmonic Reduction In Three-Phase Parallel Connected Inverter

Authors: M.A.A. Younis, N. A. Rahim, S. Mekhilef

Abstract:

This paper presents the design and analysis of a parallel connected inverter configuration of. The configuration consists of parallel connected three-phase dc/ac inverter. Series resistors added to the inverter output to maintain same current in each inverter of the two parallel inverters, and to reduce the circulating current in the parallel inverters to the minimum. High frequency third harmonic injection PWM (THIPWM) employed to reduce the total harmonic distortion and to make maximum use of the voltage source. DSP was used to generate the THIPWM and the control algorithm for the converter. Selected experimental results have been shown to validate the proposed system.

Keywords: Three-phase inverter, Third harmonic injection PWM, inverters parallel connection.

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74 Cascaded H-Bridge Five Level Inverter Based Selective Harmonic Eliminated Pulse Width Modulation for Harmonic Elimination

Authors: S. Selvaperumal, M. S. Sivagamasundari

Abstract:

In this paper, selective harmonic elimination pulse width modulation technique is employed to eliminate lower order harmonics like third by determination of solving non-linear equations. The cascaded H-bridge five level inverter is driven by the Peripheral Interface Controlled (PIC) Microcontroller 16F877A. The performance of single phase cascaded H-bridge five level inverter with relevant to harmonics and a variety of switches with solar cell as its input source is simulated by employing MATLAB/Simulink. A hardware model is developed to verify the performance of the developed system.

Keywords: Multilevel inverter, cascaded H-Bridge multilevel inverter, total harmonic distortion, selective harmonic elimination pulse width modulation, MATLAB.

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73 Effect of Flaying Capacitors on Improving the 4 Level Three-Cell Inverter

Authors: Kelaiaia Mounia Samira, Labar Hocine, Bounaya Kamel, Kelaiaia Samia

Abstract:

With the rapid advanced of technology, the industrial processes become increasingly demanding, from the point of view, power quality and controllability. The advent of multi levels inverters responds partially to these requirements. But actually, the new generation of multi-cells inverters permits to reach more performances, since, it offers more voltage levels. The disadvantage in the increase of voltage levels by the number of cells in cascades is on account of series igbts synchronisation loss, from where, a limitation of cells in cascade to 4. Regarding to these constraints, a new topology is proposed in this paper, which increases the voltage levels of the three-cell inverter from 4 to 8; with the same number of igbts, and using less stored energy in the flaying capacitors. The details of operation and modelling of this new inverter structure are also presented, then tested thanks to a three phase induction motor. KeywordsFlaying capacitors, Multi-cells inverter, pwm, switchers, modelling.

Keywords: Flaying capacitors, Multi-cells inverter, pwm, switchers, modelling.

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72 Modelling and Simulation of Cascaded H-Bridge Multilevel Single Source Inverter Using PSIM

Authors: Gaddafi S. Shehu, T. Yalcinoz, Abdullahi B. Kunya

Abstract:

Multilevel inverters such as flying capacitor, diodeclamped, and cascaded H-bridge inverters are very popular particularly in medium and high power applications. This paper focuses on a cascaded H-bridge module using a single direct current (DC) source in order to generate an 11-level output voltage. The noble approach reduces the number of switches and gate drivers, in comparison with a conventional method. The anticipated topology produces more accurate result with an isolation transformer at high switching frequency. Different modulation techniques can be used for the multilevel inverter, but this work features modulation techniques known as selective harmonic elimination (SHE).This modulation approach reduces the number of carriers with reduction in Switching Losses, Total Harmonic Distortion (THD), and thereby increasing Power Quality (PQ). Based on the simulation result obtained, it appears SHE has the ability to eliminate selected harmonics by chopping off the fundamental output component. The performance evaluation of the proposed cascaded multilevel inverter is performed using PSIM simulation package and THD of 0.94% is obtained.

Keywords: Cascaded H-bridge Multilevel Inverter, Power Quality, Selective Harmonic Elimination.

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71 FPGA Based Implementation of Simplified Space Vector PWM Algorithm for Multilevel Inverter Fed Induction Motor Drives

Authors: Tapan Trivedi, Pramod Agarwal, Rajendrasinh Jadeja, Pragnesh Bhatt

Abstract:

Space Vector Pulse Width Modulation is popular for variable frequency drives. The method has several advantages over carried based PWM and is computation intensive. The implementation of SVPWM for multilevel inverter requires special attention and at the same time consumes considerable resources. Due to faster processing power and reduced over all computational burden, FPGAs are being investigated as an alternative for other controllers. In this paper, a space vector PWM algorithm is implemented using FPGA which requires less computational area and is modular in structure. The algorithm is verified experimentally for Neutral Point Clamped inverter using FPGA development board xc3s5000-4fg900.

Keywords: Modular structure, Multilevel inverter, Space Vector PWM, Switching States.

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70 Level Shifted Carrier Signal Based Scalar Random Pulse Width Modulation Algorithms for Cascaded Multilevel Inverter Fed Induction Motor Drive

Authors: M. Nayeemuddin, T. Bramhananda Reddy, M. Vijaya Kumar

Abstract:

Acoustic noise becoming ever more obnoxious radiated by voltage source inverter fed induction motor drive in modern and industrial applications. The drive utilized for industrial and modern applications should use “spread spectrum” innovation known as Random pulse width modulation (PWM) algorithms where acoustic noise emanates through the machine should be critically concerned. This paper illustrates three types of random PWM control algorithms with fixed switching frequency namely 1) Random modulating PWM 2) Random carrier PWM and 3) Random modulating-carrier PWM. The spectrum plots of the motor stator current demonstrate the strength and robustness of the proposed PWM algorithms. To affirm the proposed algorithms, experimental tests have been conducted using dSPACE rt1104 control board on a v/f control three phase induction motor drive fed by DC link cascaded multilevel inverter.

Keywords: Multilevel inverter, acoustic noise, CSVPWM, total harmonic distortion, random PWM algorithm.

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69 Power and Delay Optimized Graph Representation for Combinational Logic Circuits

Authors: Padmanabhan Balasubramanian, Karthik Anantha

Abstract:

Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.

Keywords: AND-Inverter Graph, OR-Inverter Graph, DirectedAcyclic Graph, Low power design, Delay optimization.

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68 Heat Release Performance of Swaged- and Extruded-Type Heat Sink Used in Industrial Inverter

Authors: Jung Hyun Kim, Min Ye Ku, Gyo Woo Lee

Abstract:

In this experiment, we investigated the performance of two types of heat sink, swaged- and extruded-type, used in the inverter of industrial electricity generator. The swaged-type heat sink has 62 fins, and the extruded-type has 38 fins having the same dimension as that of the swaged-type. But the extruded-type heat sink maintains the same heat transfer area by the laterally waved surface which has 1 mm in radius. As a result, the swaged- and extruded-type heat sinks released 71% and 64% of the heat incoming to the heat sink, respectively. The other incoming heat were naturally convected and radiated to the ambient. In spite of 40% decrease in number of fins, the heat release performance of the extruded-type heat sink was lowered only 7% than that of the swaged-type. We believe that, this shows the increment of effective heat transfer area by the laterally waved surface of fins and the better heat transfer property of the extruded-type heat sink.

Keywords: Solar Inverter, Heat Sink, Forced Convection, Heat Transfer, Performance Evaluation.

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