Search results for: field-programmable gate array

Authors: Sandor Levai, Valentin Juhasz, Miklos Gasz

Abstract:

Rising damp is an extremely complex phenomenon that is of great practical interest to the field of building conservation due to the irreversible damages it can make to old and historic structures. The electrical effects occurring in damp masonry have been scarcely researched and are a largely unknown aspect of rising damp. Present paper describes the typical electrical patterns occurring in porous brickwork during a wetting and drying cycle. It has been found that in contrast with dry masonry, where electrical phenomena are virtually non-existent, damp masonry exhibits a wide array of electrical effects. Long-term real-time measurements performed in the lab on small-scale brick structures, using an array of embedded micro-sensors, revealed significant voltage, current, capacitance and resistance variations which can be linked to the movement of moisture inside porous materials. The same measurements performed on actual old buildings revealed a similar behaviour, the electrical effects being more significant in areas of the brickwork affected by rising damp. Understanding these electrical phenomena contributes to a better understanding of the driving mechanisms of rising damp, potentially opening new avenues of dealing with it in a less invasive manner.

Keywords: Brick masonry, electrical phenomena in damp brickwork, porous building materials, rising damp, spontaneous electrical potential, wetting-drying cycle.

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Authors: Astiaj Khoramshahi, Hossein Ahmadi Danesh Ashtiani, Ahmad Khoshgard, Hamidreza Damghani, Leila Damghani

Abstract:

Solar energy systems using various storages are required to be evaluated based on energy requirements and applications. Also, modeling and analysis of storage systems are necessary to increase the effectiveness of combinations of these systems. In this paper, analysis based on the MATLAB software has been analyzed to evaluate the response of the hybrid energy system considering various technologies of renewable energy and energy storage. In the present study, three different simulation scenarios are presented. Simulation output results using software for the first scenario show that the battery is effective in smoothing the overall power demand to the consumer studied during a day, but temporary loads on the grid with high frequencies, effectively cannot be canceled due to the limited response speed of battery control. Simulation outputs for the second scenario using the energy storage system show that sudden changes in demand power are paved by super saving. The majority of these sudden changes in power demand are caused by sewing consumers and receiving variable solar power (due to clouds passing through the solar array). Simulation outputs for the third scenario show the effects of the hybrid system for the same consumer and the output of the solar array, leading to the smallest amount of power demand fed into the grid, as well as demand at peak times. According to the "battery only" scenario, the displacement technique of the peak load has been significantly reduced.

Keywords: Storage system, super storage, standalone, microgrid.

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Authors: Hari Singh, Abhishek Kamboj, Sudhir Kumar

Abstract:

This investigation proposes a grey-based Taguchi method to solve the multi-response problems. The grey-based Taguchi method is based on the Taguchi’s design of experimental method, and adopts grey relational analysis (GRA) to transfer multi-response problems into single-response problems. In this investigation, an attempt has been made to optimize the drilling process parameters considering weighted output response characteristics using grey relational analysis. The output response characteristics considered are surface roughness, burr height and hole diameter error under the experimental conditions of cutting speed, feed rate, step angle, and cutting environment. The drilling experiments were conducted using L27 orthogonal array. A combination of orthogonal array, design of experiments and grey relational analysis was used to ascertain best possible drilling process parameters that give minimum surface roughness, burr height and hole diameter error. The results reveal that combination of Taguchi design of experiment and grey relational analysis improves surface quality of drilled hole. 

Keywords: Metal matrix composite, Drilling, Optimization, step drill, Surface roughness, burr height, hole diameter error.

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Authors: Minsu Seol, Youngjo Tak, Guenjai Kwak, Kijung Yong

Abstract:

ZnO heteronanostructured nanowires arrays have been fabricated by low temperature solution method. Various heterostructures were synthesized including CdS/ZnO, CdSe/CdS/ZnO nanowires and Co3O4/ZnO, ZnO/SiC nanowires. These multifunctional heterostructure nanowires showed important applications in photocatalysts, sensors, wettability control and solar energy conversion.

Keywords: ZnO nanowires, Heterostructure nanowires, solarenergy conversion, photocatalsis.

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Authors: Y. Kumru, K. Enhos, H. Köymen

Abstract:

In this paper, we report the experimental results on using complementary Golay coded signals at 7.5 MHz to detect breast microcalcifications of 50 µm size. Simulations using complementary Golay coded signals show perfect consistence with the experimental results, confirming the improved signal to noise ratio for complementary Golay coded signals. For improving the success on detecting the microcalcifications, orthogonal complementary Golay sequences having cross-correlation for minimum interference are used as coded signals and compared to tone burst pulse of equal energy in terms of resolution under weak signal conditions. The measurements are conducted using an experimental ultrasound research scanner, Digital Phased Array System (DiPhAS) having 256 channels, a phased array transducer with 7.5 MHz center frequency and the results obtained through experiments are validated by Field-II simulation software. In addition, to investigate the superiority of coded signals in terms of resolution, multipurpose tissue equivalent phantom containing series of monofilament nylon targets, 240 µm in diameter, and cyst-like objects with attenuation of 0.5 dB/[MHz x cm] is used in the experiments. We obtained ultrasound images of monofilament nylon targets for the evaluation of resolution. Simulation and experimental results show that it is possible to differentiate closely positioned small targets with increased success by using coded excitation in very weak signal conditions.

Keywords: Coded excitation, complementary Golay codes, DiPhAS, medical ultrasound.

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Authors: Li Yuan, Weizhu Wang, Kean Boon Lee, Haifeng Sun, Susai Lawrence Selvaraj, Shane Todd, Guo-Qiang Lo

Abstract:

In this work, the physical based device model of AlGaN/GaN high electron mobility transistors (HEMTs) has been established and the corresponding device operation behavior has been investigated also by using Sentaurus TCAD from Synopsys. Advanced AlGaN/GaN hetero-structures with GaN cap layer and AlN spacer have been considered and the GaN cap layer and AlN spacer are found taking important roles on the gate leakage blocking and off-state breakdown voltage enhancement.

Keywords: AlGaN/GaN, HEMT, Physical mechanism, TCAD simulation

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Authors: Tim Byrnes

Abstract:

Quantum computation using qubits made of two component Bose-Einstein condensates (BECs) is analyzed. We construct a general framework for quantum algorithms to be executed using the collective states of the BECs. The use of BECs allows for an increase of energy scales via bosonic enhancement, resulting in two qubit gate operations that can be performed at a time reduced by a factor of N, where N is the number of bosons per qubit. We illustrate the scheme by an application to Deutsch-s and Grover-s algorithms, and discuss possible experimental implementations. Decoherence effects are analyzed under both general conditions and for the experimental implementation proposed.

Keywords: Quantum, computing, information, Bose-Einstein condensates, macroscopic.

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Authors: P. Jelodarian , E. Farshidi

Abstract:

In this paper, a new approach for design of a fully differential second order current mode continuous-time sigma-delta modulator is presented. For circuit implementation, square root domain (SRD) translinear loop based on floating-gate MOS transistors that operate in saturation region is employed. The modulator features, low supply voltage, low power consumption (8mW) and high dynamic range (55dB). Simulation results confirm that this design is suitable for data converters.

Keywords: Sigma-delta, current-mode, translinear loop, geometric mean, squarer/divider.

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Authors: M. Kovac

Abstract:

This article describes design of the 8-bit asynchronous microcontroller simulation model in VHDL. The model is created in ISE Foundation design tool and simulated in Modelsim tool. This model is a simple application example of asynchronous systems designed in synchronous design tools. The design process of creating asynchronous system with 4-phase bundled-data protocol and with matching delays is described in the article. The model is described in gate-level abstraction. The simulation waveform of the functional construction is the result of this article. Described construction covers only the simulation model. The next step would be creating synthesizable model to FPGA.

Keywords: Asynchronous, Microcontroller, VHDL, FPGA.

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Authors: Seung-Mok Han, Woo-Jin Nam, Seongsoo Lee

Abstract:

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from 4×4 to 16×16 blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a 16×16 block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

Keywords: HEVC, Core transform, Low area, Shift-and-add, PE reuse

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Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang

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In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

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Authors: M. Mashayekhi, H. H. Ardakani, A. Omidian

Abstract:

Among various testing methodologies, Built-in Self- Test (BIST) is recognized as a low cost, effective paradigm. Also, full adders are one of the basic building blocks of most arithmetic circuits in all processing units. In this paper, an optimized testable 2- bit full adder as a test building block is proposed. Then, a BIST procedure is introduced to scale up the building block and to generate a self testable n-bit full adders. The target design can achieve 100% fault coverage using insignificant amount of hardware redundancy. Moreover, Overall test time is reduced by utilizing polymorphic gates and also by testing full adder building blocks in parallel.

Keywords: BIST, Full Adder, Polymorphic Gate

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

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In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor.

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Authors: Nelson K. Lujara

Abstract:

The paper presents a practical three-phase PWM inverter suitable for low voltage, low rating energy efficient systems. The work in the paper is conducted with the view to establishing the significance of the loss contribution from the PWM inverter in the determination of the complete losses of a photovoltaic (PV) arraypowered induction motor drive water pumping system. Losses investigated include; conduction and switching loss of the devices and gate drive losses. It is found that the PWM inverter operates at a reasonable variable efficiency that does not fall below 92% depending on the load. The results between the simulated and experimental results for the system with or without a maximum power tracker (MPT) compares very well, within an acceptable range of 2% margin.

Keywords: Energy, Inverter, Losses, Photovoltaic.

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Authors: P. S. Thein, S. Pramumijoyo, K. S. Brotopuspito, J. Kiyono, W. Wilopo, A. Furukawa, A. Setianto

Abstract:

In this study, we estimated the seismic ground motion parameters based on microtremor measurements atPalu City. Several earthquakes have struck along the Palu-Koro Fault during recent years. The USGS epicenter, magnitude Mw 6.3 event that occurred on January 23, 2005 caused several casualties. We conducted a microtremor survey to estimate the strong ground motion distribution during the earthquake. From this surveywe produced a map of the peak ground acceleration, velocity, seismic vulnerability index and ground shear strain maps in Palu City. We performed single observations of microtremor at 151 sites in Palu City. We also conducted8-site microtremors array investigation to gain a representative determination of the soil condition of subsurface structures in Palu City.From the array observations, Palu City corresponds to relatively soil condition with Vs ≤ 300m/s, the predominant periods due to horizontal vertical ratios (HVSRs) are in the range of 0.4 to 1.8 s and the frequency are in the range of 0.7 to 3.3 Hz. Strong ground motions of the Palu area were predicted based on the empirical stochastic green’s function method. Peak ground acceleration and velocity becomes more than 400 gal and 30 kine in some areas, which causes severe damage for buildings in high probability. Microtremor survey results showed that in hilly areas had low seismic vulnerability index and ground shear strain, whereas in coastal alluvium was composed of material having a high seismic vulnerability and ground shear strain indication.

Keywords: Palu-Koro Fault, Microtremor, Peak Ground Acceleration, Peak Ground Velocity and Seismic Vulnerability Index.

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Authors: E. Farshidi

Abstract:

This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The proposed modulator features low power consumption (<80uW), low supply voltage (1V) and 62dB dynamic range. Simulation results by HSPICE confirm that it is very suitable for low power biomedical instrumentation designs.

Keywords: Sigma-delta, modulator, Current-mode, Nonlinear Transconductance, FG-MOS.

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Authors: Abdelghani Dendouga, Nour-Eddine Bouguechal, Souhil Kouda, Samir Barra

Abstract:

A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-resistance). A comparison between the use of MOS switches and the use transmission gate switches use is analyzed.

Keywords: Charge injection, clock feed through, Sigma Deltamodulators, Sigma Delta non-idealities, switched capacitor.

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Authors: A. Karsenty, A. Chelly

Abstract:

Ultrathin (UTD) and Nanoscale (NSD) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46nm and 1.6nm respectively, were fabricated using a selective “gate recessed” process on the same silicon wafer. The electrical transport characterization at room temperature has shown a large difference between the two kinds of devices and has been interpreted in terms of a huge unexpected series resistance. Electrical characteristics of the Nanoscale device, taken in the linear region, can be analytically derived from the ultrathin device ones. A comparison of the structure and composition of the layers, using advanced techniques such as Focused Ion Beam (FIB) and High Resolution TEM (HRTEM) coupled with Energy Dispersive X-ray Spectroscopy (EDS), contributes an explanation as to the difference of transport between the devices.

Keywords: Nanoscale Devices, SOI MOSFET, Analytical Model, Electron Transport.

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Authors: M. Jagabar Sathik, K. Ramani

Abstract:

In this paper family of multilevel inverter topology with reduced number of power switches is presented. The proposed inverter can generate both even and odd level. The proposed topology is suitable for symmetric structure. The proposed symmetric inverter results in reduction of power switches, power diode and gate driver circuits and also it may further minimize the installation area and cost. To prove the superiority of proposed topology is compared with conventional topologies. The performance of this symmetric multilevel inverter has been tested by computer based simulation and prototype based experimental setup for nine-level inverter is developed and results are verified.

Keywords: Cascaded H- Bridge (CHB), Multilevel Inverter (MLI), Nearest Level Modulation (NLM), Total Harmonic Distortion (THD).

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, Kink Effect, SILVACO TCAD.

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Authors: Vasundara Patel K. S., Harsha N. Bhushan, Kiran G. Gadag, Nischal Prasad B. N., Mohmmed Haroon

Abstract:

The most widely used semiconductor memory types are the Dynamic Random Access Memory (DRAM) and Static Random Access memory (SRAM). Competition among memory manufacturers drives the need to decrease power consumption and reduce the probability of read failure. A technology that is relatively new and has not been explored is the FinFET technology. In this paper, a single cell Schmitt Trigger Based Static RAM using FinFET technology is proposed and analyzed. The accuracy of the result is validated by means of HSPICE simulations with 32nm FinFET technology and the results are then compared with 6T SRAM using the same technology.

Keywords: Schmitt trigger based SRAM, FinFET, and Static Noise Margin.

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Authors: Mazhar B. Tayel, Amr H. Yassin

Abstract:

A proposed small-signal model parameters for a pseudomorphic high electron mobility transistor (PHEMT) is presented. Both extrinsic and intrinsic circuit elements of a smallsignal model are determined using genetic algorithm (GA) as a stochastic global search and optimization tool. The parameters extraction of the small-signal model is performed on 200-μm gate width AlGaAs/InGaAs PHEMT. The equivalent circuit elements for a proposed 18 elements model are determined directly from the measured S- parameters. The GA is used to extract the parameters of the proposed small-signal model from 0.5 up to 18 GHz.

Keywords: PHEMT, Genetic Algorithms, small signal modeling, optimization.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Guo-Liang Zhang, Tai-Hong Wang

Abstract:

We propose photo-BJMOSFET (Bipolar Junction Metal-Oxide-Semiconductor Field Effect Transistor) fabricated on SOI film. ITO film is adopted in the device as gate electrode to reduce light absorption. I-V characteristics of photo-BJMOSFET obtained in dark (dark current) and under 570nm illumination (photo current) are studied furthermore to achieve high photo-to-dark-current contrast ratio. Two variables in the calculation were the channel length and the thickness of the film which were set equal to six different values, i.e., L=2, 4, 6, 8, 10, and 12μm and three different values, i.e., dsi =100, 200 and 300nm, respectively. The results indicate that the greatest photo-to-dark-current contrast ratio is achieved with L=10μm and dsi=200 nm at VGK=0.6V.

Keywords: Photo-to-dark-current contrast ratio, Photo-current, Dark-current, Process parameter

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Authors: Mojtaba Ghodsi, Hamidreza Ziaifar, Morteza Mohammadzaheri, Payam Soltani

Abstract:

In this paper, the performance of a medium power (25 kW/25 kHz) hybrid inverter with a reactive transformer is investigated. To analyze the sensitivity of the inverster, the RSM technique is employed to manifest the effective factors in the inverter to minimize current passing through the Insulated Bipolar Gate Transistors (IGBTs) (current stress). It is revealed that the ratio of the axillary inductor to the effective inductance of resonant inverter (N), is the most effective parameter to minimize the current stress in this type of inverter. In practice, proper selection of N mitigates the current stress over IGBTs by five times. This reduction is very helpful to keep the IGBTs at normal temperatures.

Keywords: Analytical analysis, hybrid resonant inverter, reactive transformer, response surface method.

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Authors: A. AlKalbany, H. Al hassan, M. Saeb

Abstract:

The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Keywords: FPGA, VHDL, micro-architecture, encryption, cryptography, algorithm, data communication security.

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Authors: M. Lenzhofer, D. Holzmann, A. Tortschanoff

Abstract:

In this paper we present a new multichannel high voltage driver box to connect up to six MOEMS mirror devices to it that have resonant and also quasistatically driven actuating electrodes. It is possible to drive all resonant axes synchronously while the amplitude of them can individually be controlled by separate microcontrollers that also operate the quasistatic axes. Circuit simulations are compared with the measurements done on the real system and also show the robust driving performance of a MOEMS mirror.

Keywords: MOEMS, scanner mirror, electrostatic driver.

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Authors: Abdelghafour Galadi

Abstract:

In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: Power MOSFET, drift layer, quasi-saturation effect, SPICE model, circuit simulation.

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Authors: Soojin Kim, Kyeongsoon Cho

Abstract:

This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

Keywords: multiplier, pipeline, high-speed, modified Boothalgorithm.

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Authors: N. Azhikhanov, T. Turimbetov, Zh. Masanov, N. Zhunisov

Abstract:

It can be determined in preference between representative mechanical and mathematical model of elasticcreeping deformation of transversally isotropic array with doubly periodic system of tilted slots, and offer of the finite elements calculation scheme, and inspection of the states of two diagonal arbitrary profile cavities of deep inception, and in setting up the tense and dislocation fields distribution nature in computing processes.

Keywords: Mathematical model, tunnel, transversally isotropic, finite elements.

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Authors: Sara Felloni, Giuliano Strini

Abstract:

We explore entanglement in composite quantum systems and how its peculiar properties are exploited in quantum information and communication protocols by means of Diagrams of States, a novel method to graphically represent and analyze how quantum information is elaborated during computations performed by quantum circuits. We present quantum diagrams of states for Bell states generation, measurements and projections, for dense coding and quantum teleportation, for probabilistic quantum machines designed to perform approximate quantum cloning and universal NOT and, finally, for quantum privacy amplification based on entanglement purification. Diagrams of states prove to be a useful approach to analyze quantum computations, by offering an intuitive graphic representation of the processing of quantum information. They also help in conceiving novel quantum computations, from describing the desired information processing to deriving the final implementation by quantum gate arrays.

Keywords: Diagrams of states, entanglement, quantum circuits, quantum information.

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