%0 Journal Article
	%A Soojin Kim and  Kyeongsoon Cho
	%D 2010
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 37, 2010
	%T Design of High-speed Modified Booth Multipliers Operating at GHz Ranges
	%U https://publications.waset.org/pdf/11040
	%V 37
	%X This paper describes the pipeline architecture of
high-speed modified Booth multipliers. The proposed multiplier
circuits are based on the modified Booth algorithm and the pipeline
technique which are the most widely used to accelerate the
multiplication speed. In order to implement the optimally pipelined
multipliers, many kinds of experiments have been conducted. The
speed of the multipliers is greatly improved by properly deciding the
number of pipeline stages and the positions for the pipeline registers to
be inserted. We described the proposed modified Booth multiplier
circuits in Verilog HDL and synthesized the gate-level circuits using
0.13um standard cell library. The resultant multiplier circuits show
better performance than others. Since the proposed multipliers operate
at GHz ranges, they can be used in the systems requiring very high
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