%0 Journal Article
	%A M. Jagabar Sathik and  K. Ramani
	%D 2014
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 95, 2014
	%T A Novel Approach of Multilevel Inverter with Reduced Power Electronics Devices
	%U https://publications.waset.org/pdf/9999847
	%V 95
	%X In this paper family of multilevel inverter topology
with reduced number of power switches is presented. The proposed
inverter can generate both even and odd level. The proposed topology
is suitable for symmetric structure. The proposed symmetric inverter
results in reduction of power switches, power diode and gate driver
circuits and also it may further minimize the installation area and
cost. To prove the superiority of proposed topology is compared with
conventional topologies. The performance of this symmetric
multilevel inverter has been tested by computer based simulation and
prototype based experimental setup for nine-level inverter is
developed and results are verified.

	%P 1773 - 1779