Power MOSFET Models Including Quasi-Saturation Effect

Authors: Abdelghafour Galadi

Abstract:

In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: Power MOSFET, drift layer, quasi-saturation effect, SPICE model, circuit simulation.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1127657

References:

[1] B. J. Baliga, “Fundamentals of Power Semiconductor Devices”, Springer, 2008.
[2] M. N. Darwish, “Study of the quasi-saturation effect in VDMOS transistors”, IEEE Trans. Electron Devices, vol. ED-33, no. 11, pp. 1710–1716, Nov. 1986.
[3] C. H. Kreuzer, N. Krischke and P. Nance, “Physically Based Description of Quasi-Saturation Region of Vertical DMOS Power Transistors”, Proc. of International Electron Devices Meeting. pp. 489 – 492, 1996.
[4] L. Wang et al., “Physical Description of Quasi-Saturation and Impact-Ionisation Effects in High-Voltage Drain-Extented MOSFETs”, IEEE Trans. Electron Devices, vol. 56, no. 3, pp 492-498, Mar. 2009.
[5] B. J. Baliga, “Advanced Power MOSFET Concepts”, Springer, 2010.
[6] T. Fujihira, “Theory of Semiconductor Superjunction Devices”, Japanese Journal of Applied Physics, 36, 6254–6262, 1997.
[7] S. C. Sun and J. D. Plummer, “Electronic Mobility Degradation in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surface”, IEEE Journal of Solid-State Circuits, vol. sc-15, no. 4, Aug. 1980.
[8] E. Seebacher et al., “High-voltage MOSFET modeling in Compact Modeling: Principles, Techniques and Applications”, Gildenblat G Ed. New York: Springer-Verlag, ch. 4 pp. 105–136, 2010.
[9] M. Mudholkar et al., “Datasheet Driven Silicon Carbide Power MOSFET Model”, IEEE trans. Power Electronics, vol. 29, no. 5, May 2014.
[10] Y. S. Chauhan et al., “A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor”, Proc. of the 7th International Symposium on Quality Electronic Design (ISQED '06), 2006.
[11] C. T. Aarts Annemarie and J. Kloosterman Willy, “Compact Modeling of High-Voltage LDMOS Devices Including Quasi-Saturation”, IEEE trans. Electron Devices, vol. 53, no. 4, pp. 897–902, Apr. 2006.
[12] B. J. Daniel, C. D. Parikh and M. B. Patil, “Modeling of the CoolMOSTM transistor-part II: DC model and parameter extraction”, IEEE trans. Electron Devices, vol. 49, pp. 923–929, May 2002.
[13] W. El Manhawy and W. Fikry 2004 “Power MOSFET Macromodel Accounting for Saturation and Quasi Saturation Effect”, Canadian Conference on Electrical and Computer Engineering, 2004.
[14] R. Vaid, N. Padha, A. Kumar, R. S. Gupta and C. D. Parikh, “Modeling power VDMOSFET transistors: Device physics and equivalent circuit model with parameter extraction”, Indian Journal of Pure & Applied Physics, vol. 42, pp. 775-782, Oct. 2004.
[15] Typical examples Available: http://www.nxp.com/technical-support-portal/#/tid=50802,sid=50933,tab=models
[16] “N-channel power MOSFET”, STP36NF06L ST datasheet, 2006. “N-channel trench power MOSFET”, HUF76419S3ST_F085 Fairchild semiconductor datasheet, 2013. “N-channel CoolMOS power Transistor”, SPW24N60C3 Infineon datasheet, 2004.
[17] T. Sakurai, A. R. Newton, “A Simple MOSFET Model for Circuit Analysis”, IEEE trans. Electron Device, vol. 38, no. 4, pp. 887-894, Apr. 1991.
[18] T. Sakurai, A. R. Newton, “Delay Analysis of Series-Connected MOSFET Circuits”, IEEE Journal of Solid state circuits, vol. 26, no. 2, pp. 112-131, Feb. 1991.
[19] A. Galadi, F. Morancho and M. M. Hassani, “A new accurate SPICE model for low-voltage power FLIMOSFETs”, Semiconductor Science and Technology, vol. 23, Apr. 2008.